Commit graph

196942 commits

Author SHA1 Message Date
Jordan Justen
ae7619429e intel/shaders: Build for Xe3
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
2024-10-26 07:39:30 +00:00
Jordan Justen
521d2299b8 intel/isl: Build for Xe3
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
2024-10-26 07:39:29 +00:00
Jordan Justen
acb1c45a8b intel/genxml: Start Xe3 support
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
2024-10-26 07:39:29 +00:00
Jordan Justen
2d15c23e4a intel/dev: Add XE3_FEATURES macro
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
2024-10-26 07:39:29 +00:00
Jordan Justen
d476badb48 intel/dev: Support Xe3 device init (for intel_device_info_test)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
2024-10-26 07:39:29 +00:00
Ian Romanick
04e1783278 brw: Call brw_fs_opt_algebraic less often
No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31729>
2024-10-25 23:39:36 +00:00
Ian Romanick
ac64b78f1f brw/copy: Perform constant folding with constant propagation
No shader-db or fossil-db changes on any Intel platform.

v2: Simlify the logic for when to try constant folding. Do
commute_immediates before constant folding. Both suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31729>
2024-10-25 23:39:36 +00:00
Ian Romanick
2cc1575a31 brw/algebraic: Refactor constant folding out of brw_fs_opt_algebraic
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31729>
2024-10-25 23:39:36 +00:00
Eric Engestrom
90ad5d3f06 ci: drop dead "load jwt in the environment just before exiting the job" code
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31855>
2024-10-25 21:41:05 +00:00
Ian Romanick
5dcad54902 brw/sat: Convert nearly all tests to use new style builders
v2: Use new style builder for second ADD in other_non_saturated_use
too.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
2024-10-25 20:31:45 +00:00
Ian Romanick
19ae7aceb5 brw/sat: Fix small typos, copy and paste, etc.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
2024-10-25 20:31:45 +00:00
Ian Romanick
de45273307 brw/builder: Add new style ALU3 builder
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
2024-10-25 20:31:45 +00:00
Ian Romanick
8329c04521 brw/copy: Don't remove instructions w/ conditional modifier
Fixes: 9e750f00c3 ("intel/brw: Make opt_copy_propagation_defs clean up its own trash")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
2024-10-25 20:31:44 +00:00
Kenneth Graunke
d949d47f09 brw/emit: Fix align16 3src subregister encodings for HF types
Prior to Cherryview, align16 3src instruction sources had to have their
subregister number be DWord-aligned.  Cherryview added a discontiguous
bit in the encoding to represent bit 1 of the subregister number.  This
allows us to use packed HF sources.

Update the ISA encoding helpers to properly handle bit 1.  While we're
at it, make them take a full subregister number and adjust accordingly,
rather than making the callers divide or multiply by some alignment.

Note that the destination subregister must still be DWord aligned, so
HF destinations must be strided.

Thanks to Ian Romanick for discovering that we were botching this.

BSpec: 12054, 12081

v2 (idr): Fix ordering of high and low bit parameters to brw_inst_bits.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
2024-10-25 20:31:44 +00:00
Kenneth Graunke
33cd5a49f1 brw/validate: Return an error for Align16 access mode on Icelake+
Gfx11+ doesn't support Align16 instructions anymore - only Align1 mode.

Bailing early for Align16 is important so that brw_hw_decode_inst
doesn't try to read Align16 related instruction fields on generations
where they no longer exist (which could trigger assertions).

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
2024-10-25 20:31:44 +00:00
Lionel Landwerlin
393ca64716 anv: avoid companion usage on RCS
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e98759c7f4 ("anv: Use RCS engine for copying stencil resource for gfx125")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31847>
2024-10-25 19:06:18 +00:00
Dmitry Osipenko
f83c2fcc98 ci/zink: Mark glx-multithread-clearbuffer flake on ADL
The glx-multithread-clearbuffer test both fails and passes depending on
a Mesa build for ADL. This test is flaky in general for everyone in Mesa,
hence move to the flakes.

Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Dmitry Osipenko
f76ed795de util/cache_test: Add mesa-db test for adding cache entry bigger than empty cache
Add Mesa-DB regression test for a segfault bug that happened when a cache
entry bigger than size-limit of the cache is added to empty cache.

Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Dmitry Osipenko
5ec424c6be util/mesa-db: Fix crash on compacting empty DB
Fix mesa_db_compact() segfaulting if compacted DB is empty. This crash
happens on writing cache entry that is bigger than DB's size limit and
when DB is empty, which can be triggered by setting DB size to a small
value.

Fixes: 32211788d0 ("util/disk_cache: Add new mesa-db cache type")
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Dmitry Osipenko
7b40d32187 util/mesa-db: Open DB files during access time
Open DB files when DB is accessed and close them afterwards to reduce
number of FDs used by multi-part DB cache.

Fixes: fd9f7b748e ("util/mesa-db: Introduce multipart mesa-db cache")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11776
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11810
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Dmitry Osipenko
2a9378a0f9 util/mesa-db-multipart: Open one cache part at a time
Open one cache DB part at a time for a multi-part cache to reduce number
of FDs used by the cache. Previously multi-part DB cache instance was
consuming 100 FDs, now it's 2 and cache files are opened when cache
is read or written instead of opening them at the init time.

Fixes: fd9f7b748e ("util/mesa-db: Introduce multipart mesa-db cache")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11776
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Dmitry Osipenko
6a2f5cb556 util/mesa-db: Fix missing O_CLOEXEC
Use O_CLOEXEC flag for opened cache DB files to not leak cache FDs when
process forks.

Fixes: 32211788d0 ("util/disk_cache: Add new mesa-db cache type")
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11810
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Michel Dänzer
92893309bc util/mesa-db: Further simplify mesa_db_compact
Taking advantage of the persistent array of index entries. In
particular, it's no longer necessary to read from the index file during
compaction.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Michel Dänzer
031f2c2a69 util: Use persistent array of index entries
Instead of allocating separate memory for each index entry in the hash
table, use a single array (backed by a mapping of anonymous memory
pages, which allows efficient array resizes) which holds a copy of the
index file contents.

The hash table now references each entry via its offset in the index
file, so that the array address can change on resize.

This eliminates some index file reads and reduces memory management
overhead for the hash table entries. It should be more efficient in
general.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Michel Dänzer
feef4bf828 util/mesa-db: Use single read for whole index
Instead of separate reads per index entry. Should be more efficient.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Michel Dänzer
1ba3996fd5 util/mesa-db: Reserve hash table for total number of index entries
Without this, the hash table needed to be rehashed about
log2(<total number of entries>) times as it grew.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Michel Dänzer
e596882dd1 util/mesa-db: Recreate files if header load or index update fails
The previous behaviour had these issues:

1. It meant that this part of the cache couldn't be used
   this time.
2. It left the corrupted index/cache files unchanged, so the same failure
   might happen again next time.

Recreating the index & cache files for this part means it can be used,
it just loses any previously cached contents.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Michel Dänzer
13c44abaac util/mesa-db: Make mesa_db_lock robust against signals
flock may be interrupted by a signal, in which case it returns with
EINTR error. In this case we need to retry until it returns success
or another error.

Fixes: 32211788d0 ("util/disk_cache: Add new mesa-db cache type")
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
2024-10-25 18:06:14 +00:00
Georg Lehmann
d01c1ba939 aco: move exec copy out of waterfall loops
Foz-DB Navi21:
Totals from 348 (0.44% of 79395) affected shaders:
CodeSize: 17944800 -> 17946268 (+0.01%); split: -0.02%, +0.03%
Latency: 29775973 -> 29774369 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 10233380 -> 10232801 (-0.01%); split: -0.01%, +0.00%

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19070>
2024-10-25 16:47:32 +00:00
Georg Lehmann
6c73a8a7f2 aco: optimize conditional divergent breaks at the end of loops
Removes one branch and one s_mov.

Foz-DB Navi21:
Totals from 1483 (1.87% of 79395) affected shaders:
Instrs: 6424114 -> 6373084 (-0.79%)
CodeSize: 35309320 -> 35091084 (-0.62%); split: -0.63%, +0.01%
Latency: 87950935 -> 88030841 (+0.09%); split: -0.03%, +0.12%
InvThroughput: 24784756 -> 24799536 (+0.06%); split: -0.02%, +0.08%
Copies: 588743 -> 561805 (-4.58%)
Branches: 242521 -> 215578 (-11.11%)
SALU: 877856 -> 850918 (-3.07%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19070>
2024-10-25 16:47:32 +00:00
Georg Lehmann
075c5818cb aco/ssa_elimination: don't assume exec writes can be removed based on block kind
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19070>
2024-10-25 16:47:32 +00:00
Georg Lehmann
61ab33c883 aco/ssa_elimination: add instr_accesses helper
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19070>
2024-10-25 16:47:32 +00:00
Valentine Burley
7ec0b62341 ir3: Don't lower to LCSSA before calling nir_divergence_analysis()
NIR can now calculate divergence without converting to LCSSA beforehand.
However, removing this particular instance of nir_convert_to_lcssa was
missed in commit 87cb42f953 ("treewide: don't lower to LCSSA before calling nir_divergence_analysis()")

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31821>
2024-10-25 16:12:51 +00:00
Valentine Burley
5bb0296e08 freedreno/devices: Establish a7xx sub-generations
We can differentiate three distinctive sub-generations on a7xx.
This reduces the number of copy-pasted quirks.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31821>
2024-10-25 16:12:51 +00:00
Valentine Burley
0981f983ee freedreno/devices: Enable 64-bit atomics on a735 and a740v3
The blob exposes VK_KHR_shader_atomic_int64 on these devices too,
but this was missed during initial enablement.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31821>
2024-10-25 16:12:51 +00:00
Valentine Burley
da989edde8 freedreno/devices: Document common name for a635 speedbins
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31821>
2024-10-25 16:12:51 +00:00
Valentine Burley
45bb8002df freedreno/devices: Inline a690 quirk
Similarly as on FD621, we only have one GPU-specific quirk, no
need to use a separate dictionary for it.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31821>
2024-10-25 16:12:51 +00:00
Rob Clark
7f63fa34da nir/lower_amul: Fix ASAN error
We shouldn't assume the bindings are sparse when we allocate an array
indexed on the binding.  See, for example:

  dEQP-GLES31.functional.program_interface_query.buffer_variable.random.55

Fixes: 2e833b16bc ("nir/lower_amul: Use num_ubos/ssbos instead of recomputing it.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31611>
2024-10-25 15:38:51 +00:00
Rob Clark
e548f90edb freedreno/ir3: Create UBO variables for driver-UBOs
Some nir passes, like lower_amul, expect to have varibles declared for
things that are accessed via load_ubo().

Fixes: 76e417ca59 ("turnip,ir3/a750: Implement consts loading via preamble")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31611>
2024-10-25 15:38:51 +00:00
Jocelyn Falempe
b24d4f0c86 gbm/dri: Fix color format for big endian.
Using wayland on s390x has all the colors wrong.
Mesa reports using GBM_FORMAT_XRGB8888 but inside the buffer, the
colors are in GBM_FORMAT_BGRX8888 order.
This patch fixes it for common formats, and also introduced BGRX8888
which is the default on big endian.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31707>
2024-10-25 14:18:24 +00:00
Jocelyn Falempe
3814dee11a gbm/dri: Use PIPE_FORMAT_* instead of using __DRI_IMAGE_*
__DRI_IMAGE formats are not well defined for big endian.
This patch has no functionnal change and prepare the work to better support
big endian.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31707>
2024-10-25 14:18:24 +00:00
Jocelyn Falempe
c6d7ab7c1f loader: Fix typo in __DRI_IMAGE_FORMAT_XBGR16161616 definition
The X and A format are inverted by mistake.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31707>
2024-10-25 14:18:24 +00:00
Pierre-Eric Pelloux-Prayer
60f7b2fc9f radeonsi/ci: mark *.tessellation_shader_tessellation.max_in_out_attributes as fixed
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31684>
2024-10-25 13:36:54 +00:00
Pierre-Eric Pelloux-Prayer
9434ac65f4 glsl: use nir_io_add_const_offset_to_base in gl_nir_opts
This fixes:
   KHR-GLES32.core.tessellation_shader.tessellation_shader_tessellation.max_in_out_attributes

Without this change the assert in gather_output is hit:
   assert(!nir_src_is_const(offset) || nir_src_as_uint(offset) == 0)

Because nir_opt_algebraic determines that some ssa values are constant,
but the nir_io_add_const_offset_to_base wasn't run afterwards.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31684>
2024-10-25 13:36:54 +00:00
Pierre-Eric Pelloux-Prayer
60578df33a nir: skip offset=0 in nir_io_add_const_offset_to_base
When offset=0, the pass was a no-op but was setting the progress
flag which could cause infinite loops when this pass is going
to be added to gl_nir_opts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31684>
2024-10-25 13:36:54 +00:00
David Rosca
f24c799c67 radeonsi/vcn: Only enable skip mode with matching references
Skip mode frames must match the reference frames otherwise skip
mode needs to be disabled.

Fixes: 1e1f078099 ("radeonsi/vcn: Add support for VCN5 AV1 compound")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31805>
2024-10-25 13:09:15 +00:00
Samuel Pitoiset
38d7492391 ci: uprev VKCTS to 1.3.10.0
This tag contains tests for DGC EXT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31789>
2024-10-25 14:03:37 +02:00
Joshua Ashton
c66fd95d92 radv: Fix sample locations at 0 for X/Y
We cannot set the {X,Y}MAX_RIGHT_EXCLUSION bits
if we have a sample location at a pixel boundary.

CTS does not seem to be catching this.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Co-authored-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31839>
2024-10-25 11:24:12 +00:00
Joshua Ashton
130a423118 radv: Enable variableSampleLocations
This should come for free now we are dynamic
rendering based.

This passes CTS on RX 7900XTX.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31839>
2024-10-25 11:24:12 +00:00
Rhys Perry
8efc765a3d nir/algebraic: fix shfr optimization with zero src2
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 08903bbe89 ("nir: add mqsad_4x8, shfr and nir_opt_mqsad")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31808>
2024-10-25 09:59:40 +00:00