20 commits

Author	SHA1	Message	Date
Caio Oliveira	c006bee22d	brw: Don't use simd_select for BS shaders ... Since there's only one possible SIMD, don't need to use the helpers to decide which one to compile. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35799>	2025-07-02 19:48:04 +00:00
Caio Oliveira	c733f07378	brw: Use the right width in brw_nir_apply_key for BS shaders ... Fixes: 23c7142cd6 ("anv: disable SIMD16 for RT shaders") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35798>	2025-07-02 15:32:23 +00:00
Caleb Callaway	e7454f5318	intel/debug: shader dump filter ... v2: Fixes filtering for various brw shader dump logic Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35061>	2025-05-23 19:57:02 +00:00
Lionel Landwerlin	06ad9a25e5	brw: fix Wa_22013689345 emission ... 2 problems : - not detecting null destination correctly - applied too late using SHADER_OPCODE_MEMORY_FENCE, when lowering already happened Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34319>	2025-04-10 16:44:28 +00:00
Lionel Landwerlin	2f156ddb50	brw: factor out base prog_data setting ... Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Michael Cheng <michael.cheng@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33643>	2025-02-22 08:30:22 +00:00
Caio Oliveira	cf3bb77224	intel/brw: Rename fs_visitor to brw_shader ... Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32536>	2025-02-11 09:13:28 +00:00
Caio Oliveira	352a63122f	intel/brw: Rename files brw_fs.cpp/h to brw_shader.cpp/h ... Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32536>	2025-02-11 09:13:28 +00:00
Caio Oliveira	f8a979466b	intel/brw: Rename and move thread_payload types to own header ... Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32536>	2025-02-11 09:13:28 +00:00
Caio Oliveira	e0614e8ea1	intel/brw: Use brw_analysis prefix for liveness analysis files ... Move declaration to the common header and rename definition file. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>	2025-02-05 21:47:06 +00:00
Caio Oliveira	92085e7bab	intel/brw: Remove 'fs' prefix from brw_from_nir functions ... Reviewed-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-by: Dylan Baker <None> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33330>	2025-02-03 23:08:11 +00:00
Francisco Jerez	dd1712515b	anv/xe3+: Set RegistersPerThread for bindless shader dispatch. ... v2: Use MOV and wrap in conditional during BTD spawn header setup (Lionel). Remove references to SIMD8 (Tapani). v3: Update brw_bsr() to specify number of registers per thread, don't initialize Registers Per Thread on BTD spawn header (Lionel). Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32664>	2025-01-29 23:39:32 +00:00
Francisco Jerez	70fecb1483	intel/brw: Report number of GRF registers used in brw_stage_prog_data. ... This is similar to what we used to do on pre-SNB platforms, the number of GRF registers used by the shader will be used on Xe3+ to adjust the trade-off between thread-level parallelism and size of the GRF file. Plumb the value through prog_data so the driver can set up the hardware state accordingly. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32664>	2025-01-29 23:39:32 +00:00
Caio Oliveira	0b310ae4d8	intel/brw: Rename fs_generator to brw_generator ... Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32844>	2025-01-17 00:04:41 +00:00
Caio Oliveira	3659934862	intel/brw: Add brw_generator.h header ... Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32844>	2025-01-17 00:04:41 +00:00
Caio Oliveira	e1aebf8a0c	intel/brw: Remove 'fs' prefix from passes and related functions ... Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32813>	2025-01-02 18:11:05 +00:00
Sviatoslav Peleshko	2a4efe21c5	intel/brw/gfx9: Implement WaClearArfDependenciesBeforeEot ... Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11928 Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31746>	2024-10-23 15:02:27 +00:00
Caio Oliveira	8a39231e4f	intel/brw: Move calculate_cfg out of fs_visitor ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30169>	2024-07-25 15:37:13 +00:00
Caio Oliveira	b98930c770	intel/brw: Move regalloc and scheduling functions out of fs_visitor ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30169>	2024-07-25 15:37:13 +00:00
Caio Oliveira	fdb029fe1b	intel/brw: Move and reduce scope of run_*() functions ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30169>	2024-07-25 15:37:13 +00:00
Caio Oliveira	c92b8a802e	intel/brw: Move remaining compile stages to their own files ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30169>	2024-07-25 15:37:13 +00:00