Commit graph

63023 commits

Author SHA1 Message Date
Eric Engestrom
aba837ef71 radv+zink/ci: add navi10 flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26135>
2023-11-09 20:59:36 +00:00
Eric Engestrom
5819e0a527 radv+zink/ci: add polaris10 flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26135>
2023-11-09 20:59:36 +00:00
Dave Stevenson
4b9e80a925 gallium: Add udl (DisplayLink) to the list of kmsro drivers
The udl is a simple render only driver, so configure it
appropriately in gallium.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26129>
2023-11-09 16:57:08 +00:00
Dave Stevenson
720c829341 gallium: Add more TinyDRM drivers to the list of kmsro drivers
As a follow-up to
8cfc17bdda ("kmsro: Add the rest of the current set of tinydrm drivers.")
and
0a42d5b98b ("kmsro: add _dri.so to two of the kmsro drivers.")
add even more TinyDRM drivers that have been added to the kernel but not
to gallium.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26129>
2023-11-09 16:57:08 +00:00
Rob Clark
b1fc5390c6 freedreno/a6xx: Fix antichamber trace replay assert
This app is generating viewports with scale[0]==0, so that is not a good
condition for testing viewport validity.  It would result in skipping
the only viewport, and ending up with gb x/y being ~0.  Triggering an
assert in the register builder.

The main reason this was done previously was to avoid an assert in
fd_calc_guardband().  Lets just flip it around and return 0x1ff on
errors instead of asserting.  This also makes it more consistent with
the other error cases.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7628
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26086>
2023-11-08 22:27:00 +00:00
Rob Clark
a9bdf58c36 freedreno/a6xx: Assume MOD_INVALID imports are linear
Without !25945 we must assume imports with invalid modifier are linear.
When both sides support metadata, we can promote the modifier.

Fixes: 33de58154f ("freedreno: Handle DRM_FORMAT_MOD_QCOM_TILED3 import")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26115>
2023-11-08 19:12:47 +00:00
Caio Oliveira
f4601d82c1 intel/compiler: Remove unused parameter from brw_nir_analyze_ubo_ranges()
This parameter was used by i965 driver that is now gone.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25986>
2023-11-08 18:10:31 +00:00
Rohan Garg
a77ea9555a blorp: WA 16014538804 for DG2, MTL A0
Send empty/dummy PIPE_CONTROL after every third 3DPRIMITIVE command.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25039>
2023-11-08 11:00:55 +00:00
Rohan Garg
1da1bcd038 iris: pull WA 22014412737 into emit_3dprimitive_was
Consolidate 3DPRIMITIVE WA's into a single function for iris

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25039>
2023-11-08 11:00:55 +00:00
Rohan Garg
8ce3b99bc1 iris: Wa 16014538804 for DG2, MTL A0
Send empty/dummy PIPE_CONTROL after every third 3DPRIMITIVE command.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25039>
2023-11-08 11:00:55 +00:00
Rohan Garg
1b03acb26b blorp,anv,iris: refactor blorp functions into something more generic
Refactor some of the blorp code into something more generic that we can
reuse for functionality needed post 3DPRIMITIVE emission.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25039>
2023-11-08 11:00:54 +00:00
Samuel Pitoiset
c2e6569b46 ci: re-apply two mesh/task query fixes for VKCTS
These are needed by RADV to enable mesh/task shader queries.

My last attempt was broken, for obscur reasons I used invalid hashes
and the dEQP build script didn't reject them. Hopefully now it should
fail if a hash is invalid.

The dEQP list changes introduced even more failures with some drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26079>
2023-11-08 07:02:27 +00:00
José Roberto de Souza
533082f384 iris: Add iris_bufmgr_get_pat_entry_for_bo_flags()
Next patches will make of intel_device_info_pat_entry parameters other
than index, so here adding a function to return it.

While at it also renaming and adjusting parameter of
iris_pat_index_for_bo_flags() to match other functions in
iris_bufmgr.c/h.

No changes in behavior expected here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26099>
2023-11-08 01:20:42 +00:00
José Roberto de Souza
29d4d26406 intel: Add more information about the PAT entry used
mmap mode information will be used to properly calculate the mmap flags
in the i915 mmap uAPI and also will be used for BO creation when the
PAT uAPI lands in Xe KMD.
Xe KMD will also require the coherency mode during the BO creation.

So to avoid information duplication, adding this information to
intel_device_info platform entries.

No changes in behavior here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26099>
2023-11-08 01:20:42 +00:00
Corentin Noël
f4ed92a823 frontends/va: Remove wrong use of ProfileToPipe
The `context->templat.profile` variable is already of enum pipe_video_profile.

Fixes: 0996ec3fc6 ("frontends/va: Add profile param when querying PIPE_VIDEO_CAP_ENC_QUALITY_LEVEL")

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26067>
2023-11-08 00:14:11 +00:00
Corentin Noël
9c78a3f5ae gallivm/lp_bld_nir_aos: Use TGSI instead of PIPE enum
Use the value from the correct enumeration.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26067>
2023-11-08 00:14:11 +00:00
Corentin Noël
91761006f6 gallivm: Initialize indir_index to NULL before use
In the case `if (var)` is false, the value will still be used but uninitialized.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26067>
2023-11-08 00:14:11 +00:00
Jesse Natalie
e61287888d d3d12: GL4.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26108>
2023-11-07 23:56:23 +00:00
Sagar Ghuge
4de0264010 iris: Disable CCS compression on top of MSAA compression on ACM
We need to manually resolve the CCS surface when it's available along
with the MSAA compression, currently we don't handle that so disable the
CCS compression for now.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26043>
2023-11-07 23:00:18 +00:00
Sagar Ghuge
e71a9e14f7 iris: Disable auxiliary buffer if MSRT is bound as texture
This change introduce the full resolve of MCS data by copying compressed
surface to uncompressed surface and also disables the auxiliary buffer
if MSRT is bound as texture on ACM platform.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26043>
2023-11-07 23:00:18 +00:00
Jesse Natalie
ba5c4da5da d3d12: Use format casting for shader images
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26104>
2023-11-07 22:31:20 +00:00
Jesse Natalie
438be4f9a0 d3d12: Support ARB_texture_view
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26104>
2023-11-07 22:31:20 +00:00
Jesse Natalie
56589cb02c d3d12: Change memory barrier implementation
Normally, we insert barriers automatically based on bind points. If
a resource is bound as both a shader image/SSBO (UAV) and other read-only
bind points, we'll choose the UAV state. This behavior is modified by
the memory barrier API - if the memory barrier indicates that a read
is desired, previously, we would've just not put any barriers to UAV
states. Now, we just use that state to disambiguate between read states
vs write states for a resource that's bound as both.

This turns out to be problematic in some circumstances, e.g.:
* PBO download, which does a memory barrier afterwards, since it uses
  shader images to write, and those might be accessed immediately as
  a texture afterwards.
* A user-issued draw that writes to a SSBO. This should indicate in the
  state tracker that the SSBO is in the UAV state.
* Some other op, like a copy, that writes to the SSBO.

Before, the "pending memory barrier" state would cause the user draw to
not be put in the UAV state, which means that the copy wouldn't issue a
barrier *out* of the UAV state, resulting in the copy being unsynchronized.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26104>
2023-11-07 22:31:20 +00:00
Jesse Natalie
3e36be7afe d3d12: Binding buffers as SSBO/storage image needs to add buffer ranges
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26104>
2023-11-07 22:31:20 +00:00
Jesse Natalie
a3899c4530 d3d12: Add a fallback for int clears where value can't be cast to float
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26104>
2023-11-07 22:31:20 +00:00
Jesse Natalie
a07bdf0152 d3d12: Initialize shader key swizzle for non-int textures
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26104>
2023-11-07 22:31:20 +00:00
Jesse Natalie
8d04efcc67 d3d12: Disable common state promotion for non-simultaneous-access textures
Work around a debug layer crash when mixing enhanced barrier layout with
non-enhanced barrier states.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26104>
2023-11-07 22:31:20 +00:00
Marek Olšák
6a31c7a841 radeonsi: move SPI_SHADER_IDX_FORMAT into the preamble (it's immutable)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
15293217e2 radeonsi: remove num_params variable from gfx10_shader_ngg
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
8edb0c7038 radeonsi: move emitting VGT_TF_PARAM into gfx10_emit_shader_ngg
so that it's next to other registers instead of separated

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
870568b512 radeonsi: prettify code around PA_SC_LINE_STIPPLE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
02f52bbca0 radeonsi: cosmetic changes in si_emit_db_render_state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
34b68c9017 radeonsi: don't check DCC compatibility on chips where it's no-op
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
ba6595e41f radeonsi: don't call nir_lower_compute_system_values too many times
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
6725edbd2a radeonsi/gfx11: use PKT3_SET_CONTEXT_REG_PAIRS_PACKED for PM4 states
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
308d3ad5c2 radeonsi: restructure blocks in si_emit_graphics_{shader,compute}_pointers
Make "if (sctx->screen->info.has_set_sh_pairs_packed) {" the outermost
condition instead of the innermost.

si_emit_consecutive_shader_pointers is split into:
- si_emit_consecutive_shader_pointers
- gfx11_push_consecutive_shader_pointers

si_emit_global_shader_pointers is split into:
- si_emit_global_shader_pointers
- gfx11_push_global_shader_pointers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
7ead9c4bb1 radeonsi: restructure blocks in si_setup_nir_user_data
From:

if (sel->info.uses_grid_size) {
   if (sctx->screen->info.has_set_sh_pairs_packed) ...
   ... else ...
}
if (sel->info.uses_variable_block_size) {
   if (sctx->screen->info.has_set_sh_pairs_packed) ...
   ... else ...
}
if (sel->info.base.cs.user_data_components_amd) {
   if (sctx->screen->info.has_set_sh_pairs_packed) ...
   ... else ...
}

To:

if (sctx->screen->info.has_set_sh_pairs_packed) {
   if (sel->info.uses_grid_size) ...
   if (sel->info.uses_variable_block_size) ...
   if (sel->info.base.cs.user_data_components_amd) ...
} else {
   if (sel->info.uses_grid_size) ...
   if (sel->info.uses_variable_block_size) ...
   if (sel->info.base.cs.user_data_components_amd) ...
}

si_cp_copy_data is moved to the beginning because it's shared.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
d26568a675 radeonsi: rewrite gfx11_*push*_sh_reg helpers
to allow reusing the macros for context registers later.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
ac22440859 radeonsi: rename radeon_*push_*_sh_reg -> gfx11_*push_*_sh_reg
Those will only be used by gfx11.x.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
4659d0dcc2 radeonsi: rename HAS_PAIRS -> HAS_SH_PAIRS_PACKED
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
626e1a01b0 radeonsi: move buffered_xx_regs into a substructure
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
df87c593f8 radeonsi: rewrite PM4 packet building helpers with less duplication
First, the following universal helpers are defined:
- radeon_set_reg_seq
- radeon_set_reg
- radeon_opt_set_reg
- radeon_opt_set_reg2
- radeon_opt_set_reg3
- radeon_opt_set_reg4
- radeon_opt_set_reg5
- radeon_opt_set_regn
- gfx11_push_sh_reg
- gfx11_opt_push_sh_reg

Then the config, context, sh, uconfig, push_gfx and push_compute helpers
are implemented calling the above.

A lot of macros were receiving sctx via a parameter, which is changed to
use sctx directly in the macro (and the parameter is renamed to "_unused").

The only functional change is that the perfctr registers that incorrectly
set the predicate bit now correctly set the RESET_FILTER_CAM bit.

The helpers no longer check info.uses_kernel_cu_mask.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
65753fa2f9 radeonsi: upload shaders using a compute queue instead of gfx
Use the original context flags when we re-create the aux contexts.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
0c773325bb radeonsi: clean up si_set_streamout_targets
Merge the branches and reorder code.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:44 +00:00
Marek Olšák
b74d849a29 ac/gpu_info: split has_set_pairs_packets into context and sh flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-07 19:27:43 +00:00
Yiwei Zhang
551f61bdb3 zink: apply can_do_invalid_linear_modifier to Venus
This unblocks Xwayland with zink-on-venus + sommelier wayland proxy.
- For glamor, zink uses linear modifier.
- For Virgl clients, classic 3d resource is used and sommelier fixes
  the modifier and stride infos no matter wl-drm or dma-buf protocol.
- For Venus clients:
  - via the legacy wl-drm protocol, invalid modifier is passed via
    sommelier, and host recovers the tiling in the way dealing with
    modifier unaware clients (e.g. I915_GEM_GET_TILING). For hosts
    unable to recover, they assume linear and venus forces linear on
    legacy path.
  - via the new zwp_linux_dmabuf_feedback_v1 (version 3/4) protocol,
    explicit modifier is used, and zink handles that without issues.

This doesn't deserve a driconfig as zink-on-venus to support xserver
itself already requires special enough integration beyond a config.

Reported-by: Igor Torrente <igor.torrente@collabora.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10066
Fixes: 1c3db3e39a ("zink: blow up broken xservers more reliably")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26082>
2023-11-07 19:00:40 +00:00
David Heidelberg
5e44cee47d ci: inject gfx-ci/linux S3 artifacts without rebuilding containers
We need update kernel often. We need test kernel changes often.

Introduced `KERNEL_EXTERNAL_TAG` to differ between `KERNEL_TAG` which is
also used to rebuild the containers. We don't need rebuild containers
for the external kernel, so this way we don't have to.

Updating kernel goes wruuuuuum.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23563>
2023-11-07 12:22:09 +00:00
David Heidelberg
b23423ce2e ci/nouveau: define a kernel and dtb, so we can fetch it from external sources
Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23563>
2023-11-07 12:22:09 +00:00
Erik Faye-Lund
385b81c8c2 panfrost: use perf_debug instead of open-coding
We don't need to open-code perf_debug here...

Fixes: bc55d150a9 ("panfrost: Add support for AFBC packing")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26063>
2023-11-07 11:07:18 +00:00
Alyssa Rosenzweig
ea6502d7cc asahi: Implement ARB_base_instance
Now that load_base_instance is wired up (as part of the indirect GS
implementation), this is really easy. Validated with Piglit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26056>
2023-11-07 00:05:55 +00:00