intel: Add more information about the PAT entry used

mmap mode information will be used to properly calculate the mmap flags
in the i915 mmap uAPI and also will be used for BO creation when the
PAT uAPI lands in Xe KMD.
Xe KMD will also require the coherency mode during the BO creation.

So to avoid information duplication, adding this information to
intel_device_info platform entries.

No changes in behavior here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26099>
This commit is contained in:
José Roberto de Souza 2023-09-05 12:13:33 -07:00 committed by Marge Bot
parent 72ba0677f8
commit 29d4d26406
5 changed files with 38 additions and 15 deletions

View file

@ -320,7 +320,7 @@ bucket_for_size(struct iris_bufmgr *bufmgr, uint64_t size,
const struct intel_device_info *devinfo = &bufmgr->devinfo;
if (devinfo->has_set_pat_uapi &&
iris_pat_index_for_bo_flags(devinfo, flags) != devinfo->pat.writeback)
iris_pat_index_for_bo_flags(devinfo, flags) != devinfo->pat.writeback.index)
return NULL;
if (devinfo->kmd_type == INTEL_KMD_TYPE_XE &&

View file

@ -547,12 +547,12 @@ iris_pat_index_for_bo_flags(const struct intel_device_info *devinfo,
unsigned alloc_flags)
{
if (alloc_flags & BO_ALLOC_COHERENT)
return devinfo->pat.coherent;
return devinfo->pat.coherent.index;
if (alloc_flags & (BO_ALLOC_SHARED | BO_ALLOC_SCANOUT))
return devinfo->pat.scanout;
return devinfo->pat.scanout.index;
return devinfo->pat.writeback;
return devinfo->pat.writeback.index;
}
enum iris_memory_zone iris_memzone_for_address(uint64_t address);

View file

@ -1136,11 +1136,9 @@ static const struct intel_device_info intel_device_info_atsm_g11 = {
.has_coarse_pixel_primitive_and_cb = true, \
.has_mesh_shading = true, \
.has_ray_tracing = true, \
.pat = { \
.coherent = 3, /* 1-way coherent */ \
.scanout = 3, /* 1-way coherent */ \
.writeback = 0, \
}
.pat.coherent = PAT_ENTRY(3, WB, 1WAY), \
.pat.scanout = PAT_ENTRY(3, WB, 1WAY), \
.pat.writeback = PAT_ENTRY(0, WB, NONE)
static const struct intel_device_info intel_device_info_mtl_u = {
MTL_FEATURES,

View file

@ -110,6 +110,31 @@ struct intel_memory_class_instance {
uint16_t instance;
};
enum intel_device_info_mmap_mode {
INTEL_DEVICE_INFO_MMAP_MODE_UC = 0,
INTEL_DEVICE_INFO_MMAP_MODE_WC,
INTEL_DEVICE_INFO_MMAP_MODE_WB,
};
enum intel_device_info_coherency_mode {
INTEL_DEVICE_INFO_COHERENCY_MODE_NONE = 0,
INTEL_DEVICE_INFO_COHERENCY_MODE_1WAY, /* CPU caches are snooped by GPU */
INTEL_DEVICE_INFO_COHERENCY_MODE_2WAY /* Fully coherent between GPU and CPU */
};
struct intel_device_info_pat_entry {
uint8_t index;
enum intel_device_info_mmap_mode mmap;
enum intel_device_info_coherency_mode coherency;
};
#define PAT_ENTRY(index_, mmap_, coh_) \
{ \
.index = index_, \
.mmap = INTEL_DEVICE_INFO_MMAP_MODE_##mmap_, \
.coherency = INTEL_DEVICE_INFO_COHERENCY_MODE_##coh_ \
}
/**
* Intel hardware information and quirks
*/
@ -462,9 +487,9 @@ struct intel_device_info
} mem;
struct {
uint8_t coherent;
uint8_t scanout;
uint8_t writeback;
struct intel_device_info_pat_entry coherent;
struct intel_device_info_pat_entry scanout;
struct intel_device_info_pat_entry writeback;
} pat;
BITSET_DECLARE(workarounds, INTEL_WA_NUM);

View file

@ -92,11 +92,11 @@ i915_gem_create(struct anv_device *device,
if (device->info->has_set_pat_uapi) {
/* Set PAT param */
if (alloc_flags & (ANV_BO_ALLOC_SNOOPED))
set_pat_param.pat_index = device->info->pat.coherent;
set_pat_param.pat_index = device->info->pat.coherent.index;
else if (alloc_flags & (ANV_BO_ALLOC_EXTERNAL | ANV_BO_ALLOC_SCANOUT))
set_pat_param.pat_index = device->info->pat.scanout;
set_pat_param.pat_index = device->info->pat.scanout.index;
else
set_pat_param.pat_index = device->info->pat.writeback;
set_pat_param.pat_index = device->info->pat.writeback.index;
intel_i915_gem_add_ext(&gem_create.extensions,
I915_GEM_CREATE_EXT_SET_PAT,
&set_pat_param.base);