This instruction is used to implement float type conversion. The source type
is defined via src1 immed (0: f32, 1: f16) and the dest type is defined via
the instruction type.
Blob generates such conv's for piglit's tests/cl/program/execute/mad-mix.cl
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30797>
This fix the HEVC encode corruption caused by mismatch between PPS
header and IB setting, the fix only apply for VCN5.
Rename from transform_skip_dicarded to transform_skip_disabled.
Signed-off-by: Yinjie Yao <yinjie.yao@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30930>
Don't claim to support extendedDynamicState3SampleLocationsEnable on pre-A650 GPUs,
which can't advertise VK_EXT_sample_locations.
Fixes dEQP-VK.info.device_mandatory_features on A6xx Gen 1 and Gen 2.
Fixes: 84726da2f4 ("tu: Implement extendedDynamicState3SampleLocationsEnable")
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30730>
The comment says, "This expands to (b & 3) & ~0xc which is (b & 3) &
3." This is not correct. ~0xc is actually 0xfffffff3.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: #11695
Fixes: 1c7e35d4e0 ("nir/algebraic: Optimize some bit operation nonsense observed in some shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30913>
Panthor support was added in Linux 6.10 and Panfrost V10
in Mesa, enabling new GPUs on Rockchip's RK3588. Add CI
jobs to test Mali V10.
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30883>
Two issues:
1. this is a baremetal/fastboot job, not a lava job, so JOB_TIMEOUT does
nothing and TEST_PHASE_TIMEOUT_MINUTES was erroneously removed
instead.
2. the test timeout needs to be smaller than the job timeout, otherwise
it can't do anything. 5min is the margin almost every job uses, so
let's use that.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30928>
It now takes ~45min (likely due to new failures being retried, itself
caused by KHR_shader_subgroup being added), but let's bump the timeout
a bit higher to avoid having to do this again soon.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30928>
(ss) can be used to resolve all tex/sfu/mem WAR hazards. However, when
the reader is a sy-producer, they can also be resolved using (sy). Track
those cases separately and make sure we don't add (ss) when the reader
has already been synced using (sy).
For example, take a sequence like this:
sam rd, rs, ...
(sy)...
(ss)write rs
Before this commit, we would add the (ss) to resolve the WAR hazard
between the consumer (sam) and the writer of rs. However, the consumer
of rs has already been synced using (sy) so has definitely consumed rs.
This commit ensures the unnecessary (ss) for the write is not added
anymore.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30611>
ir3_reg_file_offset should only be called for actual registers, not for
const or immediate values. However, this did happens accidentally for
tracking WAR hazards in ir3_legalize. While that case has been fixed,
better to prevent such cases in the future.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30611>
Sometimes not all of the jobs execute. For instance, Windows build jobs
will not trigger on AMD-only MRs. Use the 'optional' keyword to ignore
jobs which don't exist in our pipeline.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: 310e3bb026 ("ci: do not start build-only jobs until the critical build-for-tests jobs are done")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30926>
The storage allocated was always the same for both the ordinary texture
result data as well as the residency info. However, the former can be
float vector, whereas the latter is always int vector.
At least some llvm versions/builds will assert on this mismatch when
storing the data.
While here, also cut unnecessary zero initialization (lp_build_alloca()
already explicitly does this).
Fixes: 6168317b84 (lavapipe: Implement shaderResourceResidency)
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30878>
This reverts commit 3316bc3e88.
These formats were only used by RADV and are no longer needed as we can get the plane dimensions
from the YCbCr table.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30899>
This change simplifies the code by avoiding special casing, making it easier to add support
for formats like P010 with minimal changes.
Inline it on one place where where the difference for VK_FORMAT_D32_SFLOAT_S8_UINT doesn't matter.
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30899>
This change simplifies the code by avoiding special casing, making it easier to add support
for formats like P010 with minimal changes.
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30899>
Add new vk_format_get_plane_width/height helpers using ycbcr_info and use it to
replace RADV's ones which relied on util_format_get_plane_width/height.
We already have this data in the YCbCr table, so this avoids having the maintain the list
of pipe formats in util_format_get_plane_width/height.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30899>
Commit f900b763b1 we started to dirty MS as WM changes. However
later on things changed with eebb6cd236, we need to dirty with
BLEND_STATE now.
Fixes: eebb6cd236 ("anv: stop using 3DSTATE_WM::ForceThreadDispatchEnable")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30920>
Use the CLAMP macro to clamp the value and simplify the sampler count
encoding.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30922>
