Commit graph

182691 commits

Author SHA1 Message Date
Yiwei Zhang
a443d4dbc6 venus: refactor to add pipeline info fixes helpers
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26751>
2024-01-03 07:16:24 +00:00
Yiwei Zhang
c1d8056bbe venus: split up the pipeline fix description into self and pnext
prepare for fixing the pipeline pnext chain

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26751>
2024-01-03 07:16:23 +00:00
Yiwei Zhang
2e1c9b68df venus: clang format fixes
work around vk_outarray_append_typed till a better solution fits

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26751>
2024-01-03 07:16:23 +00:00
Yonggang Luo
18abdb8596 compiler/glsl: Move glsl specific _mesa_glsl_initialize_types out and glsl_symbol_table of glsl_types.h
To make sure C-ABI compat,

struct _mesa_glsl_parse_state;
struct gl_shader_program;
struct gl_builtin_uniform_desc;

are wrapped with extern "C"

And getting _mesa_glsl_initialize_variables c-compat for consistence

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26804>
2024-01-03 06:38:19 +00:00
Mark Janes
188c349e51 intel: remove workaround for preproduction DG2 steppings
DG2_G10 was released with stepping C0.
DG2_G11 was released with stepping B1.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26845>
2024-01-02 16:06:37 -08:00
Iván Briano
56d556f821 anv: enable VK_KHR_maintenance6
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
2024-01-02 22:12:02 +00:00
Iván Briano
b7c4fe54cb anv: move astc_emu to use descriptors2 calls
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
2024-01-02 22:12:02 +00:00
Iván Briano
ce6899d804 anv: add support for Cmd*DescriptorSet*2KHR
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
2024-01-02 22:12:02 +00:00
Iván Briano
40377eed91 anv: handle VkBindMemoryStatusKHR on buffer/image memory bind
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
2024-01-02 22:12:02 +00:00
Iván Briano
abe0cc8aa4 anv: remove no longer valid assert
Maintenance6 allows creating uncompressed views of compressed images
with multiple layers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
2024-01-02 22:12:02 +00:00
Iván Briano
3b5615500a anv: allow NULL index buffers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842>
2024-01-02 22:12:01 +00:00
David Heidelberg
9017852de4 ci/radeonsi: disable VA-API testing on raven
Fails and freezes after Collabora farm outage.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26820>
2024-01-02 21:33:51 +00:00
David Heidelberg
ff6589715a ci/zink: update piano trace
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26820>
2024-01-02 21:33:51 +00:00
Sergi Blanch Torne
eca667b978 Revert "ci: disable collabora farm as it is currently offline"
This reverts commit d75643f400

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26820>
2024-01-02 21:33:51 +00:00
Tapani Pälli
fe5c82e853 isl: implement Wa_14018471104
Set EnableSamplerRouteToLSC in case ResourceMinLOD is 0.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
2024-01-02 21:14:42 +00:00
José Roberto de Souza
70382f7f06 intel/isl/xe2: Enable route of Sampler LD message to LSC
Xe2 allows route of LD messages from Sampler to LSC to improve
performance when some restrictions are met.

BSpec: 57023
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
2024-01-02 21:14:42 +00:00
Zhang, Jianxun
e9b633619c intel/genxml: Add RENDER_SURFACE_STATE for xe2
The indirect BO of clear color is also removed along with clear value
address and its enabling.

Other delta in struct RENDER_SURFACE_STATE are deferred to their
functional enabling changes.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
2024-01-02 21:14:42 +00:00
Jordan Justen
db5be18862 intel/genxml/gfx125: Move STATE_SURFACE_TYPE to enum
This will allow us to use it in Xe2 genxml.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
2024-01-02 21:14:42 +00:00
Jordan Justen
772ce98a81 intel/genxml/gfx125: Move L1_CACHE_CONTROL to enum
This will allow us to use it in Xe2 genxml.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
2024-01-02 21:14:42 +00:00
Sagar Ghuge
9e97ce59a8 anv: No need to emit PIPELINE_SELECT on Xe2+
On Xe2+, PIPELINE_SELECT is getting deprecated (Bspec 55860), as a
result we don't have to do the stalling flushes while switching between
different pipelines.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26637>
2024-01-02 20:57:33 +00:00
Sagar Ghuge
a22297d2b1 iris: No need to emit PIPELINE_SELECT on Xe2+
On Xe2+, PIPELINE_SELECT is getting deprecated (Bspec 55860), as a
result we don't have to do the stalling flushes while switching between
different pipelines.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26637>
2024-01-02 20:57:33 +00:00
Karol Herbst
208875516c zink: lock screen queue on context_destroy and CreateSwapchain
Cc: mesa-stable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25985>
2024-01-02 19:40:15 +00:00
Eric Engestrom
3bff59c567 docs: fix list whitespace
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26855>
2024-01-02 17:18:34 +00:00
Eric Engestrom
ebc2af4e95 docs/backport-mr: fix invalid nested formatting
Sphinx doesn't support that, so it renders verbatim.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26855>
2024-01-02 17:18:34 +00:00
Caio Oliveira
0b5abf2512 spirv: Use value_id_bound to set initial memory allocated
Don't rely on the current default (which is 2048 bytes) buffer size for
blocks -- which ends up being too small for most shaders.  Since we
already rely on value_id_bound to allocate an array of vtn_value, use
that to estimate a better value.

In addition to space for the array, we approximate the extra size of
extra data structures with the size of vtn_ssa_value, and skip it to the
next size (double it) to cover the CFG related allocations.  This
results in only single system allocation necessary to back the temporary
data for the majority of the shaders.

Parsing code was slightly reordered so we can validate and read the
value_id_bound before the temporary allocator is created.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25279>
2024-01-02 16:07:06 +00:00
Caio Oliveira
d5b4b7356e spirv: Use linear_alloc for parsing-only data
All the vtn_* structures and arrays are used only during the lifetime of
spirv_to_nir(); we don't need to free them individually nor steal
them out; and some of them are smaller than the 5-pointer header
required for ralloc allocations.

These properties make them a good candidate for using an
arena-style allocation.

Change the code to create a linear_parent and use that for all the vtn_*
allocation.  Note that NIR data structures still go through ralloc,
since we steal them (through the nir_shader) at the end, i.e. they
outlive the parsing.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25279>
2024-01-02 16:07:06 +00:00
Caio Oliveira
89afcc94ea util: Add a way to set the min_buffer_size in linear_alloc
The default value remains 2048, which is also used for rounding up
any user provided size.

The option is useful in cases where there's a better idea of the
amount of data that's going to be used.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25279>
2024-01-02 16:07:06 +00:00
Eric Engestrom
39c8cca34f zink/requirements: update feature and property names that have been promoted
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26496>
2024-01-02 15:49:41 +00:00
Eric Engestrom
48e4c68509 zink: update symbols that have become aliases for newer ones
All of these have been renamed in the spec (usually by being promoted);
renamed them in our code too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26496>
2024-01-02 15:49:40 +00:00
Mary Guillemard
a5930b4d41 zink: Force 128 fs input components under Venus for Intel
Apply the same workaround as for Intel vk drivers by detecting Intel vendor ID.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26562>
2024-01-02 15:30:14 +00:00
Jonathan Gray
33eecafe75 zink: put sysmacros.h include under #ifdef MAJOR_IN_SYSMACROS
Fixes the build on OpenBSD, where major() is in sys/types and
sys/sysmacros.h does not exist.  Also include sys/mkdev.h if
MAJOR_IN_MKDEV is defined.

Fixes: 6d60115be7 ("zink: Fix enumerate devices when running compositor")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26735>
2024-01-02 15:11:41 +00:00
Jesse Natalie
aa81acf9cb zink: Add ASSERTED to vars that are only used for asserts
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26762>
2024-01-02 14:54:30 +00:00
Erik Faye-Lund
5024b212b6 zink: use KHR version of maint5 features
This is still not in Vulkan core, so we can't refer to it without the
KHR suffix.

Fixes: f501f9453a ("zink: use maintenance5")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26419>
2024-01-02 14:26:21 +00:00
Erik Faye-Lund
021645ebf5 zink: update profile schema
This is needed for VK_KHR_maintenance5 support.

Fixes: f501f9453a ("zink: use maintenance5")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26419>
2024-01-02 14:26:21 +00:00
Pierre-Eric Pelloux-Prayer
115b61e51f ac/surface: don't oversize surf_size
Yet another iteration on the same YUV surfaces.

The change from 87ecfdfbf0 has 2 odd things:
* it's using MAX2(original value, new value) but the point of updating
  surf_slice_size / surf_size is to make it correct relative to the new
  value of surf_pitch
* it's multiplying surf_pitch (= number of elements per row) by height (ok)
  by surf->bpe (= number of bytes per element) by surf->blk_w (= number of
  "horizontal" pixels in an element) so the end unit doesn't make sense.

Fix this by computing a reasonnable value based on unit: the surf_slice_size
is the number of elements per row (surf_pitch) x number of bytes per element
(bpe) x number of rows.

This makes the expected size correct and thus fixes users of eglCreateImageKHR,
like the issue #6131.

I tested a bunch of gst pipelines and ffmpeg scripts on various files I have
and didn't notice any issues (on gfx10.3 and gfx9).

Fixes: 87ecfdfbf0 ("ac/surface: adapt surf_size when modifying surf_pitch")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6131
Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26693>
2024-01-02 14:32:05 +01:00
Georg Lehmann
9ecfd7919b aco: optimize 32bit fsign by using fmulz with Inf
2 instruction fsign with the power of cursed DX9 floating point rules.

Foz-DB Navi31:
Totals from 3803 (4.86% of 78196) affected shaders:
Instrs: 8436366 -> 8412549 (-0.28%); split: -0.29%, +0.00%
CodeSize: 43174284 -> 43114676 (-0.14%); split: -0.14%, +0.01%
SpillSGPRs: 3241 -> 3247 (+0.19%)
Latency: 66333841 -> 66287361 (-0.07%); split: -0.08%, +0.01%
InvThroughput: 10331902 -> 10316916 (-0.15%); split: -0.15%, +0.01%
VClause: 165455 -> 165472 (+0.01%); split: -0.01%, +0.02%
SClause: 242352 -> 242335 (-0.01%); split: -0.02%, +0.01%
Copies: 604086 -> 605781 (+0.28%); split: -0.04%, +0.32%
Branches: 214017 -> 214013 (-0.00%)
PreSGPRs: 209413 -> 209726 (+0.15%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26765>
2024-01-02 13:07:30 +01:00
Mike Blumenkrantz
f60dafb4bd vulkan: add wrappers for descriptor '2' functions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26849>
2024-01-02 11:28:07 +00:00
Ganesh Belgur Ramachandra
f119f34742 radeonsi: convert "gfx11_create_sh_query_result_cs" shader to nir
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25972>
2024-01-02 10:53:31 +00:00
Ganesh Belgur Ramachandra
c109c3f95c radeonsi: convert "create_query_result_cs" shader to nir
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25972>
2024-01-02 10:53:31 +00:00
Ganesh Belgur Ramachandra
740a4c3448 radeonsi: add comments for unpack_2x16* utility functions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25972>
2024-01-02 10:53:31 +00:00
Ganesh Belgur Ramachandra
d5ef8a0ac0 radeonsi: enable nir pass for 64 bit operations
Enables optimisations for divide-by-constant which are
required in some shaders. e.g. si_create_query_result_cs()

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25972>
2024-01-02 10:53:30 +00:00
Konstantin Seurer
b88ac6b381 nir: Optimize fpow with small constant exponents
They would be turned into exp(log(a)*b) instead, which is slow.

Totals from 2146 (2.52% of 85071) affected shaders:
MaxWaves: 35769 -> 35779 (+0.03%); split: +0.03%, -0.01%
Instrs: 6476835 -> 6465494 (-0.18%); split: -0.18%, +0.00%
CodeSize: 35382288 -> 35347092 (-0.10%); split: -0.10%, +0.00%
SpillSGPRs: 1055 -> 1017 (-3.60%)
Latency: 75211743 -> 75063623 (-0.20%); split: -0.20%, +0.00%
InvThroughput: 17525115 -> 17501745 (-0.13%); split: -0.14%, +0.00%
VClause: 200089 -> 200077 (-0.01%); split: -0.01%, +0.01%
SClause: 293566 -> 293480 (-0.03%); split: -0.03%, +0.00%
Copies: 649631 -> 640516 (-1.40%); split: -1.44%, +0.03%
Branches: 268441 -> 268325 (-0.04%)
PreSGPRs: 146868 -> 146045 (-0.56%)
PreVGPRs: 134125 -> 134128 (+0.00%); split: -0.00%, +0.01%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26727>
2024-01-02 11:16:14 +01:00
Juan A. Suarez Romero
8b3496df30 ci/v3dv: update results
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26846>
2024-01-02 10:23:24 +01:00
Luca Weiss
2e46dd0624 freedreno: Enable A305B
Enable the Adreno 305B that is found on the MSM8226(v2) SoC (Snadragon
400).

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26434>
2024-01-01 20:30:46 +00:00
Mark Collins
80a319c0b4 freedreno/rddecompiler: Add ability to read GPU buffer into file
While running tests, it is be useful to have non-sequenced dumps of
certain buffers to see their contents from changes in the decompiled
CS. This introduces a function gpu_read_into_file(...) for specifying
a file to read a specific GPU buffer into after replaying the CS.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26465>
2024-01-01 18:47:48 +00:00
Mark Collins
3c89b2882f freedreno/rddecompiler: Print pkt values in hex
As most of the pkt values are arbitrarily encoded numbers, they are
less readable as integers and printing them as hex is preferable.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26465>
2024-01-01 18:47:48 +00:00
Mark Collins
84e5b28514 freedreno/rddecompiler: Reset buffers after RD_CMDSTREAM_ADDR
This is necessary to correctly decode certain traces such as those
that use FDM.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26465>
2024-01-01 18:47:48 +00:00
Mark Collins
fa735aacbf freedreno/rddecompiler: Decode ELSE branches using NOPs
In newer traces, in any cases where instructions need to be executed
for both cases of a predicate, such as for GMEM/sysmem. The proprietary
driver emits the TRUE and FALSE body one after another with a NOP at
the end of the TRUE condition body so the CP skips over the FALSE body.

Currently, the NOP skips over all instructions in the ELSE body which
results in them not being decoded whatsoever. This commit checks if
we encounter any NOPs while in a conditional block and appropriately
parses out them out into their own ELSE scope when we do.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26465>
2024-01-01 18:47:48 +00:00
Mark Collins
cfc2a85b89 freedreno/rddecompiler: Emit explicit scope for CP_COND_REG_EXEC
Due to the larger amount of conditional execution in newer traces
the flat view makes it hard to parse what might be conditionally
executed and what might now. This makes it easier to view by adding
a scope for conditionally executed commands which is indented to the
next level.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26465>
2024-01-01 18:47:48 +00:00
Rhys Perry
10e0518a85 nir/loop_analyze: remove invariance analysis
compute_invariance_information() wasn't doing anything. The only variables
not skipped in the list are phis (which are never considered invariant)
and ALU instructions which use the phi as one of it's sources.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23726>
2024-01-01 14:15:39 +00:00