Since this is no longer needed we can as well free the
memory right away instead of waiting until the parent
shader is freed.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
We don't check whether the register is overwritten between the actual
conditional test and the test of the used result, so don't try to
optimize the evaluation of the conditional.
Fixes: 79ca456b48
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
Docu says:
Ensure that the KILL* instruction is the last instruction
in an ALU clause, because the remaining instructions executed
in the clause do not reflect the updated valid state after
the kill operation.
Fixes: 79ca456b48
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
The shader key has grown substancially since the introduction of the
shadow sampler lowering to the point where passing it by value when
looking for the right variant matching the current state is showing
up in the CPU profiles. Pass the key by reference to get rid of this
overhead.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18968>
The max number of exposed fragment samplers and views on any hardware is 16,
so there is no point in having arrays of 128 entries to track information
for the shadow sampler lowering in the shader key. Most of them will never
be used. Reduce the size of the arrays to what is actually necessary and add
a assert to make sure the sampler (view) limit isn't bumped without a
matching change in the shader key.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18968>
This should make it a lot more clear how depth clip enables work.
Annoyingly, because of the way they originally worked in Vulkan 1.0,
it's dependent on the depth clamp if the state isn't set in the pipeline
and isn't declared dynamic. The enum is explicitly set up so that
drivers don't need to be aware of this change unless they already
implement VK_EXT_extended_dynamic_state3. If depth clamp/clamp are not
dynamic, depth clip will be either TRUE or FALSE which map to 1/0 so the
field can still be treated as a boolean.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18889>
and when some argument reads both from rgb and apha. We would fail to
properly rewrite the sources in such case.
Consider the following instructions:
2: src0.xyz = const[3], src1.xyz = temp[6], srcp.xyz = (src1 - src0)
CMP temp[8].x, src0.0__, src0.1__, srcp.x__
...
5: src0.xyz = const[1], src0.w = const[1]
MAX temp[10].xy, |src0.xz_|, |src0.yw_|
We can merge them together into pair like
2: src0.xyz = const[3], src1.xyz = temp[6], src2.xyz = const[1], src2.w = const[1], srcp.xyz = (src1 - src0)
MAX temp[10].xy, |src2.xz_|, |src2.yw_|
CMP temp[8].w, src0.0, src0.1, srcp.x
However the current code fails to do so properly and we end with this:
2: src0.xyz = const[3], src0.w = const[1], src1.xyz = temp[6], src2.xyz = const[1], srcp.xyz = (src1 - src0)
MAX temp[10].xy, |src2.xz_|, |src2.yw_|
CMP temp[8].w, src0.0, src0.1, srcp.x
where the src2.w is undefined.
Just check for the the case where the arguments reads both from rgb and
alpha and bail out from the merge.
Fixes the following dEQPs:
dEQP-GLES2.functional.uniform_api.random.47
dEQP-GLES2.functional.uniform_api.value.initial.render.array_in_struct.float_vec4_both
dEQP-GLES2.functional.uniform_api.value.initial.render.basic_array.vec4_both
Only a minor change in shader-db with RV530:
total instructions in shared programs: 180847 -> 180864 (<.01%)
instructions in affected programs: 3178 -> 3195 (0.53%)
helped: 2
HURT: 16
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18991>
Consistent whitespace, move var decls to first use, add some const
qualifiers, etc.
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18954>
Now the state tracker's responsible to lower away for us (and the state tracker
can do it correctly, our implementation is incorrect with a strict reading of
the Gallium contract).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18658>
The cso code hashes these as a block of bytes. This silences some
Valgrind uninitialized memory warnings and possibly avoids creating
some redundant sampler instances.
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18953>
Rejig some dirty state checks to avoid continue and make it consistent
with surrounding code.
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18953>
Maybe the frontend should map for us in this case, but it's easy enough
here: ETC2 is an extension to use undefined states from ETC1, and is
backwards compatible.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18957>
Without this, the frontend would decompress them for us without even the
kindness of a perf debug warning.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18957>
Like on adreno 3xx, hw binning and scissor optimizations don't work correctly
together on a4xx and a5xx GPUs.
Disable binning as a workaround if scissor optimizations are being used.
Fixes: f68c6951b88efaae3e19
Signed-off-by: Alejandro Tafalla <atafalla@dnyon.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18925>
On my ppc64le machine with 32 hardware threads, this speeds up OpenArena
(1920x1200) from 7.2 fps to 8.1 fps.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18415>
Some of the generic code tries to load from things it has no
types for, mip offsets, row and image strides.
Fix the interfaces to allow returning types for these.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18947>
There is too much i915_drm.h code spread, this patch start to fix that
by re-organizing engine related code.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18942>
The old code used GetElementType on a pointer, to pick a path,
I cant find a test to hit the second path, so just hardcode it
for now.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18932>
Updating accesses to refactored fields in pipe_h264_enc_picture_desc
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18877>
