Any change in .gitlab-ci/ directory triggers an entire CI run,
which is unnecessary for just changing the developers' scripts.
Added symlink to `.gitlab-ci/bin` to keep original invocation compatibility.
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20371>
We had iris_bo_alloc() call with the wrong flags value, it was
mistaken by aligment, see commit 68652dca0c.
To avoid such mistakes in future here adding BO_ALLOC_PLAIN so
iris_bo_alloc() calls have a more descriptive flag parameter when
there is no special allocation request.
While at it, also standardizing unsigned as the type for this flag.
No behavior changes here.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19857>
Port from ac_nir_to_llvm.c and si_shader_llvm_resource.c.
Due to need waterfall of llvm backend, we can't get bind-texture
descriptor directly in nir. So we keep load_sampler_desc abi only
for bind-texture index to desc.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18666>
RADV use dri option to enabled this for some apps, but it's
done in nir lower currently. I'm afraid it still needs this
option to handle the non-uniform case as desc is loaded in
llvm.
radeonsi always enable this for bind-textures.
radeonsi will lower all bind-textures to bindless-textures,
and only bind-textures use desc index, so add this abi for
bindless desc index path.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18666>
Like lower_to_fragment_fetch_amd option in lower tex,
this is for radeonsi to lower MS image ops.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18666>
Like nir_texop_fragment_mask_fetch_amd, this is used to load multi
sample image fmask data for AMD GPU.
We will lower multi sample image load and samples_identical intrinsics
to use it latter for radeonsi. RADV does not need this because it
always expand fmask images before dispatch compute shader.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18666>
Split _mesa_set_vertex_format into 2 functions and set the derived fields
after we know that the format is different.
This skips _PipeFormat and _ElementSize recomputation every time we get
gl*Pointer with the same format.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20287>
The motivation is to remove branching from prepare_indexed_draw
and remove the unsafe hack in vbo_save_playback_vertex_list.
There is some duplication that is not identical in all 3 cases.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20287>
Natively support it for virtgpu while passthrough renderer support for
vtest. This is a must support to avoid prime blit in common wsi.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20310>
Commit d08bd9a8d8 ("etnaviv: don't expose array and 3D texture support on pre-halti GPUs")
started returning 0 from PIPE_CAP_MAX_TEXTURE_2D_SIZE as well due to switch
case fallthrough. Reinstate the behavior of PIPE_CAP_MAX_TEXTURE_2D_SIZE,
while at the same time, retain the new behavior introduced by commit
d08bd9a8d8 , Otherwise not even kmscube displays the spinning cube,
weston does not display desktop and so on.
Triggered on "Vivante GC600 rev 4653" , i.MX8M Mini .
Fixes: d08bd9a8d8 ("etnaviv: don't expose array and 3D texture support on pre-halti GPUs")
Closes: #7898
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20373>
Add the GenXML hardware description for Mali architecture v10, as implemented in
Mali-G610. This is not 100% complete but it should be good enough for parity
with v9.
The XML itself is forked off of v9, with all Job Managerisms replaced with
CSFisms. This notably includes a large number of new structures defining the
instructions that run on the Command Execution Unit (CEU).
This is the first step towards supporting Mali-G610 (i.e. RK3588) upstream. Next
up will be pandecode support.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20360>
We already know from the userspace fence whether the fence has signaled
or not. No need to do a syscall if we aren't going to wait.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20263>
WC is fine for staging upload buffers, and will let us hit the default
heap. Probably introducing a separate cached-coherent heap is overkill,
and given that staging uploads are common (but downloads uncommon, out-
side of dEQP/piglit), it is better to just ask for WC.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20263>
Add a heap that we can use for allocations of small mappable buffers.
This avoids the churn of mmap/unmap, which is especially expensive in
a VM. It also allows packing more smaller allocations together in a
page, which is useful for PIPE_BUFFERs (which are also mappable).
This avoid jank caused by the overhead of setting up or tearing down
guest mappings when running in a VM. And also significantly reduces
the # of BOs referenced on a submit.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20263>
Add a way to request that allocations do not span a specified PoT
boundary. This can be used, for ex, to ensure that allocations do
not span 4GB boundaries to work around hw/fw bugs.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20263>
Remove the last fence-like-struct that isn't fd_fence. Now that
fences are refcnt'd we can just attach them directly to BOs. This
will simplify busy-ness tracking for suballoc BOs.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20263>
Now that we (a) create the fence ourselves, returning a reference from
fd_submit_flush(), and (b) refcnt the fences, we can now merge submits
with on out-fence by just attaching the same fence to all the submits.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20263>
Once we are sharing an out-fence for multiple deferred/merged submits
the complicated logic in fd_pipe_sp_flush() no longer works (or makes
sense), so just simplify all the paths into a single helper.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20263>
This moves away from embedding the submit fence inside the pipe fence,
which lets us start refcnt'ing the fence. This will enable several
cleanups and improvements:
1. Get rid of fd_bo_fence, and just have fd_bo hold pending fd_fence
refs instead, which will be needed for cpu_prep implementation of
sub-allocated buffers.
2. For merged submits, we can just return a new reference to an
existing fence.
Note that this temporarily defeats submit-merging, which will be
fixed (and improved) in a following commit.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20263>
