Commit graph

11126 commits

Author SHA1 Message Date
Pierre-Eric Pelloux-Prayer
9e76f5f2a2 radv: enable global BO list if vm_always_valid is supported
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38529>
2025-11-20 10:21:47 +00:00
Samuel Pitoiset
168a8d0b52 radv: fix RB+ for depth-only with unused attachments
When there are no color outputs in the rendering state, but color write
enable/write aren't masked out (which seems legal with
VK_EXT_dynamic_rendering_unused_attachments), the driver must emit
CB_DISABLE to disable CB rendering completely.

Otherwise, if there is also a depth/stencil attachment in the rendering
state, CB0 is always set to 32_R for RB+. That means, the pixel shader
would still export fragments but to the previously bound color
attachment.

VKCTS is missing coverage.

Fixes: 4580293ab2 ("radv: implement RB+ depth-only rendering for better perf")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14319
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38509>
2025-11-20 07:37:17 +00:00
Marek Olšák
9e339f4b32 nir: rename nir_lower_indirect_derefs -> nir_lower_indirect_derefs_to_if_else_trees
This describes better what it does.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38471>
2025-11-20 05:42:11 +00:00
Samuel Pitoiset
7c9e5b4c1c radv: remove unreachable code for prefetch in radv_cs_emit_cp_dma()
Some checks are pending
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CP DMA prefetches are implemented with a separate function.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38449>
2025-11-19 08:03:38 +00:00
Samuel Pitoiset
60d438e517 radv: always use MALL for CP DMA operations on GFX12
CP DMA isn't coherent with L2 on GFX12, but {SRC,DST}_ADDR_TC_L2 means
MALL.

Only small buffers are using copy/fill CP DMA operations, so this
shouldn't have much effect.

Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38449>
2025-11-19 08:03:38 +00:00
Samuel Pitoiset
b2a13ce92c radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38507>
2025-11-19 07:11:05 +00:00
Boris Brezillon
ea4d4d2a77 nir: Prepare nir_lower_io_vars_to_temporaries() for optional PLS lowering
Rather than adding another boolean to optionally lower PLS vars, pass
the types we want to lowers through a nir_variable_mode bitmask.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37110>
2025-11-18 20:25:42 +00:00
Samuel Pitoiset
9f512d8f93 radv: advertise VK_EXT_custom_resolve
Some checks are pending
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38442>
2025-11-18 17:03:13 +00:00
Samuel Pitoiset
91469bcc30 radv: implement VK_EXT_custom_resolve
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38442>
2025-11-18 17:03:13 +00:00
Dave Airlie
ad25196d35 radv: add support for cooperative matrix reductions.
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This add support to the lowering the reduction operations.

Thanks to Georg Lehmann for a lot of the ideas and optimising in
this.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38389>
2025-11-17 23:33:59 +00:00
David Rosca
3abb2707e2 radv/video: Fix coding used_by_curr_pic_lt_flag
Fixes: d68a1fc0d4 ("radv/video: port hevc slice header encoding from radeonsi")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14301
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38475>
2025-11-17 11:51:08 +00:00
Samuel Pitoiset
8d4ba81ca8 radv: remove now unused SDMA helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38448>
2025-11-17 11:29:24 +00:00
Samuel Pitoiset
a4e4f13c78 ac,radv: add ac_emit_sdma_copy_t2t_sub_window()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38448>
2025-11-17 11:29:24 +00:00
Samuel Pitoiset
f5ecc5ffd5 ac,radv,radeonsi: add ac_emit_sdma_copy_tiled_sub_window()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38448>
2025-11-17 11:29:24 +00:00
Samuel Pitoiset
5f8fa6ae03 ac,radv,radeonsi: add ac_emit_sdma_copy_linear_sub_window()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38448>
2025-11-17 11:29:23 +00:00
David Rosca
3858a6a696 radv/video: Fix coding allow_screen_content_tools and force_integer_mv
Some checks are pending
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This was copied from radeonsi which expected seq_force_screen_content_tools = 2
and seq_force_integer_mv = 2.

Fixes: 37e71a5cb2 ("radv/video: add support for AV1 encoding")
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38371>
2025-11-17 08:43:54 +00:00
Samuel Pitoiset
9666bd1245 radv: remove unnecessary handling of SDMA in radv_cs_emit_write_event_eop()
This function is only called for GFX or ACE. SDMA uses are already
handled before.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38430>
2025-11-17 08:28:38 +01:00
Samuel Pitoiset
6413651bcf ac,radv,radeonsi: add ac_emit_sdma_copy_linear()
RadeonSI wasn't considering the undocumented HW limitation apparently.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38430>
2025-11-17 08:28:37 +01:00
Samuel Pitoiset
191bf7aba6 ac,radv: add ac_emit_sdma_constant_fill()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38430>
2025-11-17 08:25:32 +01:00
Timur Kristóf
cad4e7d2e7 radv, radeonsi: Move GFX6-7 CB clamp issue to ac_gpu_info
To improve consistency between the two drivers.
This excludes Hawaii from the workaround on RADV.

Also add the same to ac_null_device_create().

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38304>
2025-11-15 14:24:59 +01:00
Timur Kristóf
1c8881fc60 radv: Disable sparse mapping when unsupported by VM
Also disable the sparse binding queue and other related features.
Using sparse on GFX6-8 can cause GPU hangs at the moment.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38304>
2025-11-15 14:22:49 +01:00
Marek Olšák
e372365cf4 nir: rename nir_copy_prop -> nir_opt_copy_prop
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38411>
2025-11-15 02:16:38 +00:00
Marek Olšák
482fa6818e radv: set ZMM_TRI_EXTENT for conservative rasterization == overestimate
Ported from PAL and recommended by HW people for correctness.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38434>
2025-11-14 21:18:24 +00:00
Daniel Schürmann
36b0fdb7b7 radv: move nir_opt_copy_prop_vars out of optimization loop
The effect of this change alone is >4% faster compile times.

Totals from 356 (0.45% of 79839) affected shaders: (Navi48)

Instrs: 833062 -> 817649 (-1.85%); split: -1.97%, +0.12%
CodeSize: 4387976 -> 4312616 (-1.72%); split: -1.93%, +0.22%
SpillSGPRs: 430 -> 421 (-2.09%)
LDS: 877568 -> 880640 (+0.35%)
Latency: 8862905 -> 8861517 (-0.02%); split: -0.29%, +0.28%
InvThroughput: 1470875 -> 1471874 (+0.07%); split: -0.22%, +0.28%
VClause: 16744 -> 16452 (-1.74%); split: -1.82%, +0.07%
SClause: 17583 -> 17058 (-2.99%); split: -3.04%, +0.06%
Copies: 58959 -> 58701 (-0.44%); split: -0.57%, +0.14%
Branches: 20355 -> 20276 (-0.39%); split: -0.58%, +0.20%
PreSGPRs: 21477 -> 21280 (-0.92%); split: -0.93%, +0.01%
PreVGPRs: 20596 -> 20627 (+0.15%); split: -0.27%, +0.42%
VALU: 449148 -> 440751 (-1.87%); split: -1.92%, +0.05%
SALU: 126577 -> 123978 (-2.05%); split: -2.15%, +0.09%
VMEM: 33549 -> 33559 (+0.03%); split: -1.69%, +1.72%
SMEM: 31280 -> 30543 (-2.36%); split: -2.36%, +0.00%
VOPD: 254 -> 251 (-1.18%); split: +0.39%, -1.57%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38367>
2025-11-14 09:09:15 +00:00
Daniel Schürmann
7ff8cf3e7b radv: Only call nir_lower_alu_width once in radv_optimize_nir()
No fossils stats differences.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38367>
2025-11-14 09:09:15 +00:00
Daniel Schürmann
18b99338b7 radv: don't lower_vars_to_ssa during optimization loop
Totals from 138 (0.17% of 79839) affected shaders: (Navi48)

Instrs: 129058 -> 128913 (-0.11%); split: -0.20%, +0.09%
CodeSize: 683024 -> 682056 (-0.14%); split: -0.20%, +0.06%
Latency: 1080293 -> 1080517 (+0.02%); split: -0.02%, +0.04%
InvThroughput: 180598 -> 180622 (+0.01%)
SClause: 2292 -> 2294 (+0.09%); split: -0.13%, +0.22%
Copies: 8663 -> 8721 (+0.67%); split: -2.27%, +2.94%
PreSGPRs: 5980 -> 5953 (-0.45%)
VALU: 78673 -> 78686 (+0.02%); split: -0.01%, +0.02%
SALU: 13933 -> 13860 (-0.52%); split: -1.41%, +0.89%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38367>
2025-11-14 09:09:15 +00:00
Daniel Schürmann
d959e17d3d radv: call nir_opt_find_array_copies before first radv_optimize_nir()
Totals from 11 (0.01% of 79839) affected shaders: (Navi48)

Instrs: 6514 -> 5526 (-15.17%); split: -16.76%, +1.60%
CodeSize: 34700 -> 29336 (-15.46%); split: -17.30%, +1.84%
Latency: 12372 -> 11545 (-6.68%); split: -8.13%, +1.45%
InvThroughput: 2769 -> 2444 (-11.74%); split: -12.96%, +1.23%
Copies: 738 -> 649 (-12.06%)
Branches: 155 -> 111 (-28.39%)
PreVGPRs: 506 -> 471 (-6.92%); split: -7.71%, +0.79%
VALU: 3467 -> 2915 (-15.92%); split: -16.96%, +1.04%
SALU: 992 -> 839 (-15.42%); split: -16.03%, +0.60%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38367>
2025-11-14 09:09:14 +00:00
Daniel Schürmann
bf0e04a531 radv: Only call nir_opt_dead_write_vars once
Totals from 2 (0.00% of 79839) affected shaders: (Navi48)

Instrs: 5540 -> 5524 (-0.29%)
CodeSize: 27536 -> 27424 (-0.41%)
Latency: 37602 -> 37526 (-0.20%)
InvThroughput: 9401 -> 9382 (-0.20%)
Copies: 839 -> 845 (+0.72%); split: -0.12%, +0.83%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38367>
2025-11-14 09:09:14 +00:00
Daniel Schürmann
c3b72ea00c radv: Only call nir_opt_memcpy once
No fossil stats differences.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38367>
2025-11-14 09:09:14 +00:00
Samuel Pitoiset
e47a60255a radv: add a workaround for color<->stencil only copies on SDMA4-5
Some checks are pending
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For weird reasons, on SDMA4-5 color<->stencil only copies don't work
correctly. I compared NAVI21 (SDMA 5) vs NAVI31 (SDMA 6), everything
is bits-to-bits exact but the same test doesn't pass on NAVI21. So,
it's potentially a hardware bug on SDMA < 6.

Fixes dEQP-VK.api.ds_color_copy.*_tq on GFX9-GFX10.3.

Fixes: 0034f5a948 ("radv: allow ds<->color copies on compute/transfer queues")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38377>
2025-11-14 06:57:57 +00:00
Benjamin Cheng
8848495875 radv/video: Align each layer of encode DPB to 256
VCN requires the luma/chroma VAs to be 256 aligned. On VCN5, the
collocated buffer was not 256 aligned which can cause these VAs to be
unaligned.

This fixes VVL PositiveVideoEncodeH264.Basic on VCN5.

Fixes: 37e71a5cb2 ("radv/video: add support for AV1 encoding")
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38408>
2025-11-13 17:18:50 +00:00
Benjamin Cheng
b4ae11ee42 ac,radeonsi/vcn,radv/video: Drop signature param
The signature is not very useful, and is unnecessary CPU overhead.

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38372>
2025-11-13 14:35:58 +00:00
Samuel Pitoiset
9141696d32 radv: fix gathering push constants from shaders with ESO
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Need to be 4-bytes aligned.

Fixes: aa44a5a4ae ("radv: gather push constant size from shaders for ESO")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14276
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38397>
2025-11-13 07:30:14 +00:00
Samuel Pitoiset
388875abe1 radv: bump maxRayDispatchInvocationCount to 2^30
It's the required limit by Vulkan.

Fixes dEQP-VK.ray_tracing_pipeline.limits.ray_tracing_props.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38405>
2025-11-13 07:10:39 +00:00
Yonggang Luo
ecb0ccf603 treewide: Replace calling to function ALIGN with align
This is done by grep ALIGN( to align(

docs,*.xml,blake3 is excluded

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38365>
2025-11-12 21:58:40 +00:00
Konstantin Seurer
de32f9275f treewide: add & use parent instr helpers
We add a bunch of new helpers to avoid the need to touch >parent_instr,
including the full set of:

* nir_def_is_*
* nir_def_as_*_or_null
* nir_def_as_* [assumes the right instr type]
* nir_src_is_*
* nir_src_as_*
* nir_scalar_is_*
* nir_scalar_as_*

Plus nir_def_instr() where there's no more suitable helper.

Also an existing helper is renamed to unify all the names, while we're
churning the tree:

* nir_src_as_alu_instr -> nir_src_as_alu

..and then we port the tree to use the helpers as much as possible, using
nir_def_instr() where that does not work.

Acked-by: Marek Olšák <maraeo@gmail.com>

---

To eliminate nir_def::parent_instr we need to churn the tree anyway, so I'm
taking this opportunity to clean up a lot of NIR patterns.

Co-authored-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38313>
2025-11-12 21:22:13 +00:00
Samuel Pitoiset
6cf1f3b39a radv: fix supporting more tess parameters with TCS for ESO unlinked shaders
Some checks are pending
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VGT_OUTPRIM_TYPE should be programmed correctly when PointMode is only
set in TCS with ESO.

Fixes dEQP-VK.shader_object.tessellation.hlsl.point_mode.

Fixes: c6d9b9b4e0 ("radv: support more tessellation parameters with TCS for ESO unlinked shaders"
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38376>
2025-11-12 16:21:17 +00:00
Samuel Pitoiset
75a1380355 radv: add RADV_DEBUG=dumpibs to dump command buffers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38366>
2025-11-12 08:52:17 +00:00
Samuel Pitoiset
842603dc4f radv/amdgpu: add a way to identify preamble/postamble when dumping CS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38366>
2025-11-12 08:52:17 +00:00
Autumn Ashton
2705d8bd8b radv/video: Implement VK_VALVE_video_encode_rgb_conversion
This is used by Steam Link VR (driver_vrlink) to avoid doing YUV conversion itself.

Signed-off-by: Autumn Ashton <misyl@froggi.es>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37500>
2025-11-12 08:25:36 +00:00
Natalie Vock
73a31dafbc radv: Fix PSO history with RT pipelines
1. The prolog needs to have a null check. Libraries don't have prologs.
2. We only need to print the shaders actually included in this pipeline.
   Libraries were already printed separately.
3. The traversal shader was wrongly omitted from the output.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38355>
2025-11-12 08:00:54 +00:00
Samuel Pitoiset
0dba538643 radv/meta: fuse depth/stencil aspects copy with the GFX path
Depth/stencil copies on graphics are twice as fast now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38139>
2025-11-12 07:35:33 +00:00
Samuel Pitoiset
9d3dd174b8 radv/meta: rework radv_meta_nir_texel_fetch_build_func
This add a binding parameter that will be used for fused depth/stencil
copies.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38139>
2025-11-12 07:35:33 +00:00
Samuel Pitoiset
332f881375 radv/meta: simplify aspect/formats in radv_gfx_copy_image()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38139>
2025-11-12 07:35:32 +00:00
Samuel Pitoiset
cd59db45f9 radv/meta: simplify radv_gfx_copy_memory_to_image() even more
Selecting formats can be simplified.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38139>
2025-11-12 07:35:32 +00:00
Samuel Pitoiset
ed05c3fc31 radv/meta: remove multiple aspects in radv_gfx_copy_memory_to_image()
Only one aspect at any time is valid.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38139>
2025-11-12 07:35:31 +00:00
Samuel Pitoiset
a1884dc737 radv/meta: remove radv_meta_blit2d_rect
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38139>
2025-11-12 07:35:31 +00:00
Samuel Pitoiset
1319b2bef6 radv/meta: split radv_meta_blit2d() into two separate functions
It's more code but it's definitely easier to read and it will allow us
to do more cleanups/optimizations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38139>
2025-11-12 07:35:30 +00:00
Samuel Pitoiset
bb3f69fefe radv/meta: remove useless blit2d_src_temps
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38139>
2025-11-12 07:35:29 +00:00
Daniel Schürmann
5682e39e6b amd: enable load/store_shared2_amd for GFX6
Totals from 1509 (2.43% of 62200) affected shaders: (Pitcairn)

MaxWaves: 8078 -> 8057 (-0.26%); split: +0.09%, -0.35%
Instrs: 977182 -> 951746 (-2.60%); split: -2.62%, +0.02%
CodeSize: 4951468 -> 4758192 (-3.90%); split: -3.92%, +0.01%
SGPRs: 76704 -> 76696 (-0.01%)
VGPRs: 81092 -> 81068 (-0.03%); split: -0.34%, +0.31%
Latency: 11663237 -> 11526070 (-1.18%); split: -1.19%, +0.01%
InvThroughput: 6198904 -> 6114851 (-1.36%); split: -1.43%, +0.07%
VClause: 26656 -> 26655 (-0.00%); split: -0.05%, +0.05%
SClause: 22304 -> 22307 (+0.01%); split: -0.03%, +0.04%
Copies: 107503 -> 109564 (+1.92%); split: -0.23%, +2.15%
Branches: 22917 -> 22918 (+0.00%)
PreSGPRs: 42246 -> 42242 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 64561 -> 64761 (+0.31%); split: -0.01%, +0.32%
VALU: 600285 -> 601139 (+0.14%); split: -0.26%, +0.40%
SALU: 130622 -> 130851 (+0.18%); split: -0.16%, +0.33%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37682>
2025-11-11 17:12:17 +00:00