Create svga_framebuffer_state as a subclass of pipe_framebuffer_state.
This contains pointers to svga_surface objects which correspond to
pipe_framebuffer_state's surfaces.
Replace pipe_surface with svga_surface in many functions.
Stop using deprecated util_framebuffer_init() function.
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/13262
Signed-off-by: Brian Paul <brian.paul@broadcom.com>x
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35238>
The util_copy_framebuffer_state() function copies the width, height,
nr_cbufs fields.
Also move a loop variable.
Signed-off-by: Brian Paul <brian.paul@broadcom.com>
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35238>
The number of columns should never be less than 1, otherwise we can
break the script such as:
```
Traceback (most recent call last):
File "/var/home/guilherme/projects/mesa/bin/ci/ci_run_n_monitor.py", line 734, in <module>
main()
File "/var/home/guilherme/projects/mesa/bin/ci/ci_run_n_monitor.py", line 713, in main
target_job_id, ret, exec_t = monitor_pipeline(
^^^^^^^^^^^^^^^^^
File "/var/home/guilherme/projects/mesa/bin/ci/ci_run_n_monitor.py", line 221, in monitor_pipeline
cancel_jobs(project, to_cancel)
File "/var/home/guilherme/projects/mesa/bin/ci/ci_run_n_monitor.py", line 400, in cancel_jobs
print_formatted_list(cancelled_jobs, indentation=8)
File "/var/home/guilherme/projects/mesa/bin/ci/gitlab_gql.py", line 373, in print_formatted_list
step = (len(elements) // n_columns) + 1
~~~~~~~~~~~~~~^^~~~~~~~~~~
ZeroDivisionError: integer division or modulo by zero
```
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35250>
Applications using Mesa built with LLVM 20.1.4 fail to start with
strange segmentfaults/bus errors when radeonsi driver is used. The last
piece of stacktrace looks like
- pipe_reference_described
- pipe_reference
- radeon_bo_reference
- radeon_ws_bo_reference
- radeon_lookup_or_add_real_buffer
Coredump shows the pointer dst passed to pipe_reference_described() is
either unaligned or even invalid, which is the reason of crashing. The
crash goes away when Mesa is built without optimization.
Looking through the related functions, it's found that
radeon_ws_bo_reference() contains unsafe type cast from radeon_bo to
pb_buffer_lean: though the former's first field is just the later, this
violates strict aliasing rules as pb_buffer_lean isn't compatible with
radeon_bo. Such violation ultimately results in miscompilation.
Let's take the address of pb_buffer_lean field, avoiding the unsafe
cast. It's still required to cast pb_buffer_lean back to radeon_bo since
radeon_bo_reference may update the pointer, which is safe as radeon_bo
contains a pb_buffer_lean member and C language permits access members
through a pointer in type of the container.
Fixes: 6d913a2bcc ("r300,r600,radeonsi: switch to pb_buffer_lean")
Link: https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Aliasing-Type-Rules.html
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35249>
With older FW this needs to be always enabled, but it can now be
disabled when using the new separate header instructions for
dependent_slice_segment_flag and slice_segment_address.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35072>
We create hierarchy masks based on the number of levels available,
creating a bitmask with `max_levels` bits set. Originally these bits
all came together. Modify this to spread the bits out, which improves
performance on chips like the G31 with only 2 levels of hierarchy.
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34744>
PRE_POST_FRAME_SHADER_MODE_EARLY_ZS_ALWAYS was introduced in
architecture version 7.2, not 7.0 as we assumed. Using it on
G31 (a 7.0 device) caused some CTS failures.
Cc: mesa-stable
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34744>
Using MemScope::System synchronizes with everything, which is exactly
what we don't want for constant loads. This is currently a no-op
because we aren't using MemScope::Constant pre-Ampere yet.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35217>
Internal shaders can also use slm, so we need to allocate it correctly.
This fixes
dEQP-VK.dgc.ext.compute.misc.max_pc_range_256_full_preprocess_with_execution_set
with NAK_DEBUG=spill
Fixes: 105bdf2e36 ("nvk: Add a helper for dispatching compute shaders")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35143>
It's very common needing to extract or overwrite a certain field
in an already packed register value, so add macros to do that
instead of manually doing that each time.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35088>
In panfrost_clear_depth_stencil and panfrost_clear_render_target, we
start the blit context before binding the clear targets. If we don't
legalize AFBC beforehand, we get a recursive blit crash. panfrost_clear
does not need this because the resource should already be legalized in
panfrost_batch_add_surface.
Fixes the following piglit tests with pan_force_afbc_packing:
- spec@arb_clear_texture@arb_clear_texture-base-formats
- spec@arb_clear_texture@arb_clear_texture-simple
- spec@arb_clear_texture@arb_clear_texture-sized-formats
Fixes: 17a62ff993 ("panfrost: legalize afbc before blitting")
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34992>
