The delivered values in the coarse pixel size are 0 when coarse pixel
dispatch is disabled and that is screwing up our half pixel offset
adjustment.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36457>
When building for C23 the compiler warns about returning a boolean when
a different type is expected instead.
Change the code to return NULL instead of false, fixing the following
error:
-----------------------------------------------------------------------
../src/intel/vulkan_hasvk/anv_nir_apply_pipeline_layout.c: In function ‘nir_deref_find_descriptor’:
../src/intel/vulkan_hasvk/anv_nir_apply_pipeline_layout.c:230:14: error: incompatible types when returning type ‘_Bool’ but ‘nir_intrinsic_instr *’ {aka ‘struct nir_intrinsic_instr *’} was expected
230 | return false;
| ^~~~~
-----------------------------------------------------------------------
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36323>
Retrieving memory requirement size and alignment via
anv_image_get_memory_requirements() return's 0 before surfaces are added
by resolve_anb_image() and will assert in align64() when align is 0:
Abort message: '../src/util/u_math.h:713: uint64_t align64(uint64_t, uint64_t): assertion "util_is_power_of_two_nonzero64(alignment)" failed'
Refactor out anv_image_bind_from_gralloc() into resolve_anb_image() so
the checks are performed after the surface is adds.
Resolving also requires API 29 so return VK_ERROR_EXTENSION_NOT_PRESENT
without it.
Fixes: 43cb986d9e ("anv/android: resolve ANB swapchain images on bind")
Signed-off-by: Juston Li <justonli@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36060>
Xe2 adds two more flags registers. We barely use the second flags
register on previous platforms, so the omission was not previously
noticed.
There are several efforts in progress that will add using of more flags
registers.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35415>
At this point, using the per-register granularity will only help in
conjuction with fragment shader discard (which is implemented using f1).
v2: Loop restructuring and code cleanups. Suggested by Curro.
v3: Only apply Wa on Gfx12.5+. Suggested by Curro.
v4: Also apply to implicit flag reads. Suggested by Curro. This version
affects a *lot* more shaders (10,936 on Meteor Lake shader-db versus
4,482 before). The results are still very much in the 🤷 territory.
v5: Add missing dependency. I thought I got them all the previous
time. :( Noticed by Curro.
shader-db:
Lunar Lake
total cycles in shared programs: 886315282 -> 886391040 (<.01%)
cycles in affected programs: 204907250 -> 204983008 (0.04%)
helped: 1 / HURT: 6716
LOST: 0
GAINED: 1
Meteor Lake and DG2 had similar results. (Meteor Lake shown)
total cycles in shared programs: 883774789 -> 883921507 (0.02%)
cycles in affected programs: 481836784 -> 481983502 (0.03%)
helped: 4 / HURT: 10936
LOST: 3
GAINED: 7
fossil-db:
Lunar Lake
Totals:
Cycle count: 32600441334 -> 32601862658 (+0.00%); split: -0.00%, +0.00%
Totals from 90283 (11.44% of 789260) affected shaders:
Cycle count: 17265933202 -> 17267354526 (+0.01%); split: -0.00%, +0.01%
Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Cycle count: 26477292677 -> 26480321805 (+0.01%); split: -0.00%, +0.01%
Max dispatch width: 8010440 -> 8010984 (+0.01%)
Totals from 132952 (14.71% of 903925) affected shaders:
Cycle count: 15349555348 -> 15352584476 (+0.02%); split: -0.00%, +0.02%
Max dispatch width: 1085416 -> 1085960 (+0.05%)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35415>
Keep the support in gen_sort_xml.py to allow it still convert
old MRs into the new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
And change the gen_sort_xml.py script to default to the new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
Change code to temporarily support both the start/end old format and the
dword/bits new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
Add a `--bits-format` argument to normalize the output to either of the
formats described below. For now, defaults to the old format.
The documentation in PRMs and BSpec describe the fields with the dword
and the bit range. Using the same convention makes easier to spot
issues.
Old format:
```
<field name="Disable SLM Read Merge Optimization" start="38" end="38" type="bool" />
<field name="Pixel Async Compute Thread Limit" start="39" end="41" type="uint" prefix="PACTL">
```
New format:
```
<field name="Disable SLM Read Merge Optimization" dword="1" bits="6:6" type="bool" />
<field name="Pixel Async Compute Thread Limit" dword="1" bits="9:7" type="uint" prefix="PACTL">
```
For Groups, we store the dword and if needed a offset_bits, in case
a group starts in a non-aligned position. Size and count for groups are
not changed.
Do this first for gen_sort_tags.py in case is convenient to have for the
stable tree to convert future patches from the new back into the old
format. Later patches will add support to the rest of the code.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
Avoid noise when changing to the new GenXML field format -- which would
try to also sort it. Also add this file to be checked as part of tests.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
The Xe kernel driver doesn't allow vm_bind on compressed bo
if it has user pointer. And we probably shouldn't enable CCS
compression on memory in any case.
This change is necessary to prevent failures once we adjust the
priority of compression PAT entries in a following commit:
Vulkan CTS:
dEQP-VK.api.buffer_marker.compute.external_host_mem.top_of_pipe.
memory_dep.buffer_copy
dEQP-VK.memory.external_memory_host.simple_allocation.
minImportedHostPointerAlignment_x3
anv_kmd_backend.c:308: xe_vm_bind_op: Assertion
`errno_ != EINVAL' failed.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36275>
Tested with:
commit 3a252ff9d8b6dc22b20463bfcb31a4e8992b0e8f
Merge: 9800bf6fae3b 11895f375939
Author: Simona Vetter <simona.vetter@ffwll.ch>
Date: Fri Jul 11 11:25:34 2025 +0200
Note that the kernel treats WCL similar to PTL, so 94de1dfd4729
("drm/xe/ptl: Drop force_probe requirement") also removed the
force_probe for WCL.
Backport-to: 25.1
Ref: 3c0f211bc8fc ("drm/xe: Add Wildcat Lake device IDs to PTL list")
Ref: 94de1dfd4729 ("drm/xe/ptl: Drop force_probe requirement")
Ref: drm/drm-next 3a252ff9d8b6dc22b20463bfcb31a4e8992b0e8f
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36148>
Allow CCS for non-display linear surfaces in isl_surf_supports_ccs().
We're going to rely more on the helper to determine CCS-enabling for Xe2
on iris.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32120>
The compression format is only used during rendering.
This prevents drivers from hitting an unreachable when we start enabling
CCS on linear surfaces which may have non-renderable and non-pow2 formats.
For now, continue to use the surface format instead of the view format
to look up the CMF. This strategy should return the optimal CMF for
compressed surfaces that undergo redescription during copies.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32120>
for intrinsics, we have these really nice builders using designated initializers
+ macros to specify optional indices. texture instrs have even more craziness
involved, but we can do the same trick. this commit takes the existing "fixed
form" deref-centric tex builders and generalizes them to work with non-deref
textures, making it useful also for GL and late VK passes, while providing an
API that strives to be ergonomic and consistent.
this series only implements a subset of possible texture operations for now, but
more generalizing could be added as people have need.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36050>
Replace uses of brw_builder::at() with various more descriptive
variants. Use block pointer from instruction when possible.
A couple of special cases remained and will be handled in separate patches.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34681>
The HW only supports converting BRW_TYPE_BF values to/from BRW_TYPE_F,
so intermediate conversion is needed. Move the intermediate conversion
to the implementation of `@convert_cmat_intel` and simplify the
brw_nir_lower_cooperative_matrix pass. This has two positive effects
- Fixes conversion between BF and integer type cooperative matrices,
that was still using the old emit_alu1 approach instead of the new
code for `@convert_cmat_intel`.
- Guarantee the intermediate conversion will result in a valid layout
for conversions involved USE_B matrices. If we instead used the
intrinsic twice in brw_nir_lower_cooperative_matrix.c, a matrix with
invalid layout would be visible at NIR level and we wouldn't be able
to keep the current assertion for USE_B case.
Due to the configurations we have exposed, we still don't need to
write a more complex USE_B conversion -- they are all between same
size types (and, consequently, packing factors), so no shuffling of
data is needed to respect the USE_B layout.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36185>
Logical sends and load_payload can have large VGRFs that cannot be
split. Once all of the lowering passes and optimization passes that
might eliminate any of those instructions have completed, try to split
larger VGRFs one last time.
Register allocation can only handle VGRFs up to a certain size, so this
is the last opportunity to prevent later failures due to VGRFs that are
too large.
Closes: #13239
shader-db:
Lunar Lake, Meteor Lake, DG2, and Tiger Lake had similar results. (Lunar Lake shown)
total instructions in shared programs: 17114494 -> 17114496 (<.01%)
instructions in affected programs: 2790 -> 2792 (0.07%)
helped: 2 / HURT: 4
total cycles in shared programs: 886617364 -> 886315282 (-0.03%)
cycles in affected programs: 4067540 -> 3765458 (-7.43%)
helped: 48 / HURT: 9
Ice Lake and Skylake had similar restuls. (Ice Lake shown)
total instructions in shared programs: 20799801 -> 20799691 (<.01%)
instructions in affected programs: 1210 -> 1100 (-9.09%)
helped: 1 / HURT: 0
total cycles in shared programs: 865495386 -> 865498990 (<.01%)
cycles in affected programs: 60132 -> 63736 (5.99%)
helped: 2 / HURT: 1
total spills in shared programs: 3987 -> 3981 (-0.15%)
spills in affected programs: 24 -> 18 (-25.00%)
helped: 1 / HURT: 0
total fills in shared programs: 3535 -> 3519 (-0.45%)
fills in affected programs: 36 -> 20 (-44.44%)
helped: 1 / HURT: 0
fossil-db:
All Intel platforms had similar results. (Lunar Lake shown)
Totals:
Instrs: 208647246 -> 208646499 (-0.00%); split: -0.00%, +0.00%
Cycle count: 31257819536 -> 31263957016 (+0.02%); split: -0.02%, +0.04%
Max live registers: 66160877 -> 66155728 (-0.01%)
Totals from 34703 (4.91% of 707053) affected shaders:
Instrs: 13766639 -> 13765892 (-0.01%); split: -0.02%, +0.01%
Cycle count: 3693572086 -> 3699709566 (+0.17%); split: -0.15%, +0.32%
Max live registers: 4843852 -> 4838703 (-0.11%)
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36202>
In debug builds, the assertion should be preferred as it will highlight
the actual problem. In non-debug builds, it is possible to fail register
allocation more gracefully. If the problem only occurs in, for example,
a SIMD32 version of a shader, the application may even continue to
function.
Closes: #13239
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36202>
So that the body field has the same name in COMPUTE_WALKER &
EXECUTE_INDIRECT_DISPATCH.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36146>
Broadcast selects one lane from the source to write to all the lanes
of the destination. This makes it possible for the first half to
overwrite the source used by the second half.
No shader-db changes on any Intel platform.
fossil-db:
Lunar Lake
Totals:
Instrs: 208705405 -> 208705374 (-0.00%); split: -0.00%, +0.00%
Cycle count: 31274597098 -> 31273711544 (-0.00%); split: -0.00%, +0.00%
Totals from 77 (0.01% of 707133) affected shaders:
Instrs: 220177 -> 220146 (-0.01%); split: -0.02%, +0.00%
Cycle count: 461694212 -> 460808658 (-0.19%); split: -0.33%, +0.14%
No fossil-db changes on any other Intel platforms.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35903>
