Commit graph

96822 commits

Author SHA1 Message Date
Ilia Mirkin
92f56fbd89 nvc0: fix blitting red to srgb8_alpha
For some reason the 2d engine can't handle this. Red formats get special
treatment there, so perhaps related.

Fixes dEQP-GLES3 tests of the form:

  dEQP-GLES3.functional.fbo.blit.conversion.r{8,16f,32f}_to_srgb8_alpha8

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
2018-10-09 10:33:11 -04:00
Ilia Mirkin
9bf0614116 nv50,nvc0: guard against zero-size blits
The current state tracker can generate these sometimes. Fixing this is
more involved, and due to some integer math we can generate
divisions-by-zero.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
2018-10-09 10:33:11 -04:00
Ilia Mirkin
78d3640e49 nv50,nvc0: mark RGBX_UINT formats as renderable
This helps st/mesa avoid some (apparently) buggy fallbacks. Specifically
the CopyTexSubImage fallback tries to read texture A as RGBA_FLOAT and
write back that data into the target format, which fails for integer
formats which have no appropriate logic to do the conversion.

Since integer formats don't blend, there's no harm in the fact that the
"A" component gets written anyways.

Fixes, among others:
  https://www.khronos.org/registry/webgl/sdk/tests/conformance2/textures/canvas/tex-2d-rgb8ui-rgb_integer-unsigned_byte.html

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2018-10-09 10:33:11 -04:00
Eric Engestrom
976188737d radv: add missing meson c++ visibility arguments
Fixes: 6f3aee40f9 "radv: using tls to store llvm related info
                             and speed up compiles (v10)"
Cc: Dave Airlie <airlied@redhat.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-10-09 14:22:24 +01:00
Michel Dänzer
9d3fefdc41 gbm: Add GBM_FORMAT_ARGB1555 support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-09 10:32:51 +02:00
Michel Dänzer
e7e033ed8a st/dri: Handle BGRA5551 format
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-09 10:32:50 +02:00
Rob Clark
fa52ff856d freedreno/a5xx+a6xx: fix LRZ pitch alignment
Both RB_2D_DST_SIZE.PITCH (a6xx) and RB_MRT[n].PITCH (a5xx) need
alignment to 64.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 19:05:14 -04:00
Rob Clark
82c3b6fe49 freedreno/a6xx: add LRZ support
As with a5xx, hidden behind FD_MESA_DEBUG=lrz due to being paranoid
about z-fighting issues with some games (in particular, this was
observed with 0ad on a5xx.. but I think the proper solution to enable
this by default is to figure out how to do driver specific driconf
options).

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 19:05:14 -04:00
Rob Clark
a877451a41 freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 18:03:35 -04:00
Rob Clark
bf79a7cc25 freedreno/a6xx: add helper for various CP_EVENT_WRITE
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 17:50:26 -04:00
Rob Clark
60af89815e freedreno/a6xx: remove unused fxns
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 17:50:26 -04:00
Rob Clark
d5bd3ce89c freedreno/a6xx: remove fd6_shader_stateobj
Earlier gen's already got this cleanup, but a6xx was still off on a
branch then.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08 17:50:26 -04:00
Ilia Mirkin
1bb1c03d61 glsl: fix array assignments of a swizzled vector
This happens in situations where we might do

  vec.wzyx[i] = ...

The swizzle would get effectively ignored because of the interaction
between how ir_assignment->set_lhs works and overwriting the write_mask.
There are two cases, one where i is a constant, and another where i is
variable. We have to be extra-careful in both cases.

Fixes the following WebGL test:

  https://www.khronos.org/registry/webgl/sdk/tests/conformance2/glsl3/vector-dynamic-indexing-swizzled-lvalue.html

And the new piglit tests:

  swizzled-writemask-indexing-nonconst.shader_test
  swizzled-writemask-indexing.shader_test

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
2018-10-08 14:29:14 -04:00
Samuel Pitoiset
d3682766f6 radv: tidy up radv_pipeline_init_multisample_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08 14:17:43 +02:00
Samuel Pitoiset
b38228ccb0 radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK
It has probably no effect without out of order rasterization
anyway.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08 14:17:40 +02:00
Samuel Pitoiset
937986ca1d radv: set DB_EQAA.INCOHERENT_EQAA_READS
My attempt was to set this field instead of duplicating one.

Fixes: 6cfa321c39 ("radv: add potential missing fields for DB_EQAA")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08 14:17:33 +02:00
Chystiakov, Dmytro
47e3338b04 i965: fallback RGBX to RGBA in glEGLImageTargetRenderbufferStorageOES
In the same fashion as is done for glEGLImageTextureTarget2D.

v2: share the fallback which sets baseformat and internalformat correctly
    which makes both of the tests pass (Tapani)

Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests:

   #SingleLayer_ColorTest_GpuColorOutputCpuRead_R8G8B8X8_UNORM
   #SingleLayer_ColorTest_GpuColorOutputIsRenderable_R8G8B8X8_UNORM

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-08 08:03:45 +03:00
Tapani Pälli
d1fa69ed61 glsl: do not attempt assignment if operand type not parsed correctly
v2: check types of both operands (Ian)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108012
2018-10-08 08:02:50 +03:00
Marek Olšák
d877451b48 util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
Initial version discussed with Rob Clark under a different patch name.
This approach leaves his driver unaffected.
2018-10-06 22:05:58 -04:00
Marek Olšák
066aa44fc5 radeonsi: fix a typo at CS_PARTIAL_FLUSH
harmless
2018-10-06 21:50:52 -04:00
Marek Olšák
77903c8cfb ac: add ac_build_round 2018-10-06 21:50:09 -04:00
Marek Olšák
fa023f293e ac: correct PKT3_COPY_DATA definitions 2018-10-06 21:50:09 -04:00
Marek Olšák
82f5f89bf6 ac: simplify LLVM alloca helpers 2018-10-06 21:50:09 -04:00
Marek Olšák
a668c8d6ba ac: define all address spaces properly 2018-10-06 21:50:09 -04:00
Gert Wollny
8f77156c26 gallivm: Make it possible to disable some optimization shortcuts in release builds
For testing it is of interest that all tests of dEQP pass, e.g. to test
virglrenderer on a host only providing software rendering like in a CI.
Hence make it possible to disable certain optimizations that make tests fail.

While we are there also add some documentation to the flags to make it clear
that this is opt-out.

Setting the environment variable "GALLIVM_PERF=no_filter_hacks" can be used to make
the following tests pass in release mode:

  dEQP-GLES2.functional.texture.mipmap.2d.affine.*_linear_*
  dEQP-GLES2.functional.texture.mipmap.cube.generate.*
  dEQP-GLES2.functional.texture.vertex.2d.filtering.*_mipmap_linear_*
  dEQP-GLES2.functional.texture.vertex.2d.wrap.*

Related:
  https://bugs.freedesktop.org/show_bug.cgi?id=94957

v2: rename optimization disabling flag to 'safemath' and also move the
    nopt flag to the perf flags.

v3: rename flag "safemath" to "no_filter_hacks" since safemath is usually
    associated with floating point operations (Roland)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-10-06 13:12:48 +02:00
Tomeu Vizoso
9d81cd8e7c virgl: Pass resource size and transfer offsets
Pass the size of a resource when creating it so a backing can be kept in
the other side.

Also pass the required offset to transfer commands.

This moves vtest closer to how virtio-gpu works, making it more useful
for testing.

v2: - Use new messages for creation and transfers, as changing the
      behavior of the existing messages would be messy given that we don't
      want to break compatibility with older servers.

v3: - Use correct strides: The resource corresponding to the output display
      might have a differnt line stride then the IOVs, so when reading back
      to this resource take the resource stride and the the IOV stride
      into account.

v4: Fix transfer size calculation (Andrey Simiklit)

v5: Add comment about transfer size value in the PUT commend (Gurchetan).
    Add a comment about the size correction for transfers for reading and
    writing the resource. Fixing this by correctly evaluating the size
    upfront will need some work also  on the virglrenderer side.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> (v2)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-06 13:12:44 +02:00
Gert Wollny
5d7858f151 virgl, vtest: Correct the transfer size calculation
The transfer size used in virglrenderer refers to uint32_t, so one
must add 3 and then divide by 4 instead of adding 3/4 which is a no-op
with integers.

Fixes: b3b82fe8ea virgl/vtest: add vtest driver

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-06 13:12:44 +02:00
Alan Coopersmith
066850edad util: Make xmlconfig.c build on Solaris without d_type in dirent (v2)
v2: check for lstat() failing

Fixes: 04bdbbcab3 "xmlconfig: read more config files from drirc.d/"
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Reviewed-by: Roland Mainz <roland.mainz@nrubsig.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-05 17:30:45 -07:00
Sonny Jiang
084cf3b966 radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuse
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang
ce1d72609d radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang
4de328da07 radeonsi:optimizing SET_CONTEXT_REG for shaders PS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang
f243980f2c radeonsi:optimizing SET_CONTEXT_REG for shaders VS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Sonny Jiang
4052624398 radeonsi:optimizing SET_CONTEXT_REG for shaders GS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 19:04:13 -04:00
Marek Olšák
86f004bdfc radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functions
reg_saved will have 64 bits, and (1 << reg) where reg > 31 has undefined
behavior. (1ull << reg) would be correct for 64 bits.

This commit shifts the other way in order to merge the conditions.
2018-10-05 19:04:13 -04:00
Sonny Jiang
eeb9170599 radeonsi: optimizing SET_CONTEXT_REG for shaders ES
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05 17:53:52 -04:00
Samuel Pitoiset
a1bc152340 spirv: mark variables decorated with XfbBuffer as always active
Otherwise, they are removed during NIR linking or in some
lowering passes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-10-05 18:13:25 +02:00
Jason Ekstrand
dd553bc67f nir/alu_to_scalar: Use ssa_for_alu_src in hand-rolled expansions
The ssa_for_alu_src helper will correctly handle swizzles and other
source modifiers for you.  The expansions for unpack_half_2x16,
pack_uvec2_to_uint, and pack_uvec4_to_uint were all broken with regards
to swizzles.  The brokenness of unpack_half_2x16 was causing rendering
errors in Rise of the Tomb Raider on Intel ever since c11833ab24
which added an extra copy propagation to the optimization pipeline and
caused us to start seeing swizzles where we hadn't seen any before.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107926
Fixes: 9ce901058f "nir: Add lowering of nir_op_unpack_half_2x16."
Fixes: 9b8786eba9 "nir: Add lowering support for packing opcodes."
Tested-by: Alex Smith <asmith@feralinteractive.com>
Tested-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2018-10-04 12:43:59 -05:00
Vadym Shovkoplias
5f0567a4f6 glsl/linker: Check the subroutine associated functions names
>From Section 6.1.2 (Subroutines) of the GLSL 4.00 specification

    "A program will fail to compile or link if any shader
     or stage contains two or more functions with the same
     name if the name is associated with a subroutine type."

v2:
  - error out earlier (Tapani)
  - style fixes (Iago)

Fixes:
    * no-overloads.vert

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108109
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-10-04 17:41:19 +02:00
Tomeu Vizoso
ed53a79cf8 virgl: Negotiate version with vtest server
Check if server supports version negotation by sending a PING_PROTOCOL_VERSION
message right before a dummy RESOURCE_BUSY_WAIT. If we don't get a reply
for the first, we know the server doesn't support it.

If it does support it, we can query the max protocol version supported
by the server and fall back if needed.

v2: - Send a new message to negotiate the protocol version, checking if
      the server supports this message by immediately sending a busy wait
      message. (Dave Airlie)

v3: - Send a zero-arg command PING_PROTOCOL_VERSION so we actually keep
      compatibility with older servers. (Code by Dave Airlie)

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-04 16:18:36 +02:00
Sagar Ghuge
0c70e11206 intel: aubinator: Fix memory leaks
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-04 10:01:56 +01:00
Sagar Ghuge
29a2eaf3db intel/decoder: construct correct xml filename
construct correct gen xml filename when we try to load hardware xml
description from a given path

v2: remove temporary variable (Francesco Ansanelli)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-04 10:01:56 +01:00
Sagar Ghuge
f9c8468c82 intel/decoder: Avoid freeing invalid pointer
v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin)

v3: Handle case where genxml is empty (Lionel Landwerlin)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-04 10:01:56 +01:00
Sagar Ghuge
ba3304e764 intel/decoder: add gen_spec_init method
Initialize gen_spec instance properly when loading hardware xml
description from specifc directory to avoid segmentation fault.

v2: correct function definition (Lionel Landwerlin)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-04 10:01:56 +01:00
Samuel Pitoiset
2b34985d93 radv: fix resetting the pool for timestamp queries
Since the driver no longer uses the availability bit for
timestamp queries it shouldn't reset it. Instead, it should
reset the query values to UINT32_MAX. This fixes VM faults.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108164
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-10-04 10:56:25 +02:00
Guido Günther
b2a876a42b etnaviv: Use write combine instead of unached mappings for shader bo
The later are sensitive to unaligned accesses on arm64[1] and we don't
need an uncached mapping here.

[1]: https://lists.freedesktop.org/archives/etnaviv/2018-September/001956.html

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-10-04 10:33:25 +02:00
Marek Olšák
8e0b4cb8a1 drirc: add a workaround for ARMA 3
Cc: 18.2 <mesa-stable@lists.freedesktop.org>
2018-10-04 01:01:54 -04:00
Jason Ekstrand
f5bab06428 anv/batch_chain: Don't start a new BO just for BATCH_BUFFER_START
Previously, we just went ahead and emitted MI_BATCH_BUFFER_START as
normal.  If we are near enough to the end, this can cause us to start a
new BO just for the MI_BATCH_BUFFER_START which messes up chaining.  We
always reserve enough space at the end for an MI_BATCH_BUFFER_START so
we can just increment cmd_buffer->batch.end prior to emitting the
command.

Fixes: a0b133286a "anv/batch_chain: Simplify secondary batch return..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107926
Tested-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-03 09:03:12 -05:00
Jason Ekstrand
7a89a0d9ed anv: Use separate MOCS settings for external BOs
On Broadwell and above, we have to use different MOCS settings to allow
the kernel to take over and disable caching when needed for external
buffers.  On Broadwell, this is especially important because the kernel
can't disable eLLC so we have to do it in userspace.  We very badly
don't want to do that on everything so we need separate MOCS for
external and internal BOs.

In order to do this, we add an anv-specific BO flag for "external" and
use that to distinguish between buffers which may be shared with other
processes and/or display and those which are entirely internal.  That,
together with an anv_mocs_for_bo helper lets us choose the right MOCS
settings for each BO use.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99507
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-03 09:03:03 -05:00
Emil Velikov
fe8be81b4a Revert "mesa: remove unnecessary 'sort by year' for the GL extensions"
This reverts commit 3d81e11b49.

As reported by Federico, some games require the 'sort by year' since
they truncate the extensions which do not fit the fixed size string
array.

Seemingly I did not consider that, as the documentation (both Mesa and
Nvidia) mentions about program crashes ... which are worked around by
setting the env. variable.

This commit reinstates the workaround and enhances the documentation.

Cc: Marek Olšák <maraeo@gmail.com>
Cc: Ian Romanick <idr@freedesktop.org>
Reported-by: Federico Dossena <info@fdossena.com>
Fixes: 3d81e11b49 ("mesa: remove unnecessary 'sort by year' for the GL
extensions")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Federico Dossena <info@fdossena.com>
2018-10-03 13:38:06 +01:00
Emil Velikov
91ff8b1dd9 mesa: reorder and document the tokens in glheader.h
Split into different sections, document each one as well as strange
cases like GL_ATI_texture_compression_3dc.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-03 13:38:06 +01:00