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Author SHA1 Message Date
Alyssa Rosenzweig
904760ff8e radv/nir_lower_fs_intrinsics: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig
184557932f radv/nir_lower_intrinsics_early: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig
a589bae3aa radv/nir_lower_fs_barycentric: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig
88587a3839 radv/nir_lower_view_index: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig
c025a211f2 radv/nir_lower_viewport_to_zero: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig
2504e7951b treewide: use nir_shader_tex_pass 
Adapted the Coccinelle rules from the nir_shader_intrinsics_pass commit a while
ago, which was buggy then and buggy now, so then I fixed stuff up manually
(including formatting).

Via Coccinelle patch:

    @def@
    typedef bool;
    typedef nir_builder;
    typedef nir_instr;
    typedef nir_def;
    identifier fn, instr, intr, x, builder, data;
    @@

    static fn(nir_builder* builder,
    -nir_instr *instr,
    +nir_tex_instr *intr,
    ...)
    {
    (
    -   if (instr->type != nir_instr_type_tex)
    -      return false;
    -   nir_tex_instr *intr = nir_instr_as_tex(instr);
    |
    -   nir_tex_instr *intr = nir_instr_as_tex(instr);
    -   if (instr->type != nir_instr_type_tex)
    -      return false;
    )

    <...
    (
    -instr->x
    +intr->instr.x
    |
    -instr
    +&intr->instr
    )
    ...>

    }

    @pass depends on def@
    identifier def.fn;
    expression shader, progress;
    @@

    (
    -nir_shader_instructions_pass(shader, fn,
    +nir_shader_tex_pass(shader, fn,
    ...)
    |
    -NIR_PASS_V(shader, nir_shader_instructions_pass, fn,
    +NIR_PASS_V(shader, nir_shader_tex_pass, fn,
    ...)
    |
    -NIR_PASS(progress, shader, nir_shader_instructions_pass, fn,
    +NIR_PASS(progress, shader, nir_shader_tex_pass, fn,
    ...)
    )

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v3d]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
Georg Lehmann
940e87f225 nir/opt_remove_phis: use nir_shader_phi_pass 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
Georg Lehmann
e4f0de89a5 nir/opt_phi_precision: use nir_shader_phi_pass 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
Georg Lehmann
5a0702f351 nir/builder: add nir_shader_phi_pass 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
Alyssa Rosenzweig
dda2dadb98 nir/builder: add nir_shader_tex_pass 
after the intrinsic and ALU passes. why not?

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
David Rosca
367735551d frontends/vdpau: Use extra reference buffer for AV1 film grain 
AV1 applies film grain to decode target only, references in DPB must be
stored without film grain.
Fixes film grain decoding on drivers that use decode target buffers
directly for references.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33640>
 2025-02-24 19:04:53 +00:00
Georg Lehmann
5da76df4cd nir/search_helpers: check tex source type in is_only_used_as_float 
Foz-DB Navi21:
Totals from 164 (0.21% of 79377) affected shaders:
Instrs: 197477 -> 197035 (-0.22%); split: -0.23%, +0.01%
CodeSize: 1052944 -> 1051140 (-0.17%); split: -0.18%, +0.01%
VGPRs: 8104 -> 8080 (-0.30%)
Latency: 1115663 -> 1115567 (-0.01%); split: -0.06%, +0.05%
InvThroughput: 265822 -> 265158 (-0.25%); split: -0.26%, +0.01%
VClause: 3792 -> 3789 (-0.08%); split: -0.11%, +0.03%
SClause: 5738 -> 5744 (+0.10%); split: -0.02%, +0.12%
Copies: 12223 -> 12200 (-0.19%); split: -0.53%, +0.34%
PreVGPRs: 6807 -> 6801 (-0.09%); split: -0.15%, +0.06%
VALU: 139206 -> 138785 (-0.30%); split: -0.31%, +0.01%
SALU: 27852 -> 27853 (+0.00%)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33674>
 2025-02-24 16:34:53 +00:00
Georg Lehmann
3d8585e4fc nir/search_helpers: look through vecs in is_only_used_as_float 
Will be useful with the next commit, or for backends that don't lower
alu to scalar.

No changes on Navi21.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33674>
 2025-02-24 16:34:53 +00:00
Georg Lehmann
e0cebac14f nir/opt_algebraic: optimize b2f(a != 0) * a 
Just D3D9 things.

Foz-DB Navi21:
Totals from 137 (0.17% of 79377) affected shaders:
MaxWaves: 3366 -> 3370 (+0.12%); split: +0.24%, -0.12%
Instrs: 76462 -> 72091 (-5.72%)
CodeSize: 411584 -> 380792 (-7.48%)
Latency: 279472 -> 275505 (-1.42%); split: -2.01%, +0.59%
InvThroughput: 71311 -> 65369 (-8.33%)
VClause: 1587 -> 1612 (+1.58%); split: -1.01%, +2.58%
SClause: 1111 -> 1105 (-0.54%); split: -1.08%, +0.54%
Copies: 5621 -> 5602 (-0.34%); split: -1.39%, +1.05%
PreSGPRs: 5266 -> 5241 (-0.47%); split: -0.51%, +0.04%
PreVGPRs: 4249 -> 4236 (-0.31%); split: -0.35%, +0.05%
VALU: 50049 -> 45901 (-8.29%)
SALU: 8948 -> 8818 (-1.45%)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33674>
 2025-02-24 16:34:53 +00:00
Mike Blumenkrantz
e63acdd2b7 zink: force cached mem for streaming uploads 
it was previously possible to hit a path where an idle buffer with
non-cached mem could be directly mapped for streaming data uploads,
which kills perf

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33678>
 2025-02-24 15:55:21 +00:00
Job Noorman
7210054db8 ir3: reformat after previous commit 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33701>
 2025-02-24 15:27:12 +00:00
Job Noorman
2fedc82c0c ir3: don't use deprecated NIR_PASS_V anymore 
Also replace OPT_V with OPT while we're at it.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33701>
 2025-02-24 15:27:12 +00:00
Job Noorman
0f69ada3b5 ir3/lower_tess: make all NIR passes report progress 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33701>
 2025-02-24 15:27:11 +00:00
Thomas H.P. Andersen
7276191d59 nvk: use a valid allocation scope 
VK_OBJECT_TYPE_DESCRIPTOR_POOL is used in vk_zalloc2 as allocation scope.
This should probably have been object scope.

Fixes: 607686f6bf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33697>
 2025-02-24 14:44:33 +00:00
Rhys Perry
2a3dce1b59 ac/nir: fix tess factor optimization when workgroup barriers are reduced 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: b49eab68a8 ("ac/nir: use s_sendmsg(HS_TESSFACTOR) to optimize writing tess factors for gfx11")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12632
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33645>
 2025-02-24 14:07:40 +00:00
Valentine Burley
5a510aede7 anv/ci: Increase parallelism of zink-anv-adl 
With some of the jobs migrated to the new brask and nissa devices, we can
increase zink-on-anv coverage on brya. Reduce the fraction of Piglit
tests and introduce fractional GLESCTS testing.

Also increase the parallelism of the zink nightly job, but lower its
FDO_CI_CONCURRENT variable to avoid OOMkills. To accommodate this,
decrease the parallelism of the anv-adl-full job.

Additionally, drop redundant HWCI_START_WESTON from full runs that
inherit the variable from their pre-merge jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley
318bc2ef03 intel/ci: Migrate intel-adl-cl and intel-adl-skqp to nissa 
Move the piglit CL and SKQP jobs to the new nissa devices. Nissa is
significantly slower than brya, so increase parallelism and timeout
accordingly.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley
cb9875ce1b anv/ci: Migrate anv-adl-angle job to brask 
Move the ANGLE job to the new brask devices. Brask is significantly
slower than brya, so increase the parallelism accordingly.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley
2a3c373824 intel/ci: Add brask and nissa 
Add two new device types in LAVA, brask and nissa. These ADL devices will
be used to offload some of the jobs from brya.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley
85f9088d13 intel/ci: Honor device-specific FDO_CI_CONCURRENT variables 
FDO_CI_CONCURRENT was getting overwritten by .intel-common-test
inheriting FDO_CI_CONCURRENT: 6 from .lava-test, so change the order of
these definitions to fix that.

This change unfortunantely means that GPU_VERSION has to be overwritten
in some cases.

Additionally, drop redundant .anv-test where .anv-angle-test is used.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley
38fc58107a anv/ci: Update expectations from latest nightly 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Daniel Schürmann
ea765162c3 aco/ssa_elimination: create a single parallelcopy instruction for linear and logical phis 
Totals from 6651 (8.38% of 79377) affected shaders: (Navi31)

Instrs: 14722896 -> 14722290 (-0.00%); split: -0.01%, +0.00%
CodeSize: 77992072 -> 77989284 (-0.00%); split: -0.01%, +0.00%
Latency: 160542885 -> 160541215 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 24543177 -> 24542710 (-0.00%); split: -0.00%, +0.00%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33527>
 2025-02-24 13:11:20 +00:00
Daniel Schürmann
0e98388614 aco/ssa_elimination: refactor scratch_sgpr handling 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33527>
 2025-02-24 13:11:20 +00:00
Daniel Schürmann
302678df91 aco/ssa_elimination: insert parallelcopies for p_phi immediately before branch 
Totals from 2499 (3.15% of 79377) affected shaders: (Navi31)
Instrs: 6011729 -> 6011761 (+0.00%); split: -0.00%, +0.00%
CodeSize: 31573216 -> 31574236 (+0.00%); split: -0.00%, +0.00%
Latency: 83364734 -> 83365781 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 13545643 -> 13545783 (+0.00%); split: -0.00%, +0.00%

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33527>
 2025-02-24 13:11:20 +00:00
Daniel Schürmann
794c2b7e2f aco/lower_branches: allow other instructions after s_andn2 in break blocks 
We are about to insert parallelcopies from phis there.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33527>
 2025-02-24 13:11:20 +00:00
Daniel Schürmann
115ff5f95b aco/insert_exec_mask: don't restore exec in continue_or_break blocks 
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33527>
 2025-02-24 13:11:20 +00:00
Daniel Schürmann
7f7c1d463a aco/insert_exec_mask: Don't immediately set exec to zero in break/continue blocks 
Instead, only indicate that exec should be zero and do
so in the successive helper block. This allows to insert
the parallelcopies from logical phis directly before the
branch in break and continue blocks.

Totals from 56 (0.07% of 79377) affected shaders: (Navi31)
Latency: 2472367 -> 2472422 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 253053 -> 253055 (+0.00%); split: -0.00%, +0.00%

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33527>
 2025-02-24 13:11:20 +00:00
Karol Herbst
4975ac79ef rusticl/util: add missing comment and assert to char_arr_to_cstr 
I forgot to push those changes...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33703>
 2025-02-24 12:23:21 +00:00
Lionel Landwerlin
e4f31b8744 intel/ds: rework RT tracepoints 
That way we can identify single dispatch within each step.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Michael Cheng <michael.cheng@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33684>
 2025-02-24 08:08:02 +00:00
Lionel Landwerlin
31c5c386d1 u_trace: pass tracepoint flags to the read_timestamp callback 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Michael Cheng <michael.cheng@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33684>
 2025-02-24 08:08:02 +00:00
Yiwei Zhang
43c3270c26 venus: temporarily disable 1.4 support 
Will implement VK_EXT_host_image_copy via custom venus protocol support
and then re-enable 1.4.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33698>
 2025-02-24 00:11:55 +00:00
Yiwei Zhang
ac13146092 venus: limit second queue emulation to android framework 
A proper emulation of a second queue requires handling of
wait-before-signal behavior of timeline semaphore. It's doable in Venus
but not that much useful since 1.4 requires a second transfer queue
family if not implementing hostImageCopy. So this change has limited
the second queue emulation as a workaround for android framework on
Android 14 and above.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33698>
 2025-02-24 00:11:55 +00:00
Karol Herbst
0fd70ee9de rusticl/platform: advertise all extensions supported by all devices 
There is a spec issue about this to clarify this behavior, but the current
wording can be interpreted that the platform always lists all extensions
supported by all drivers.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33667>
 2025-02-23 19:39:58 +00:00
Mi, Yanfeng
ed77f67e44 anv: add emulated 64bit integer storage support 
By turning a R64 into R32G32

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:51 +00:00
Mi, Yanfeng
723e52cbcc anv: Support putting image base address and image params in surface state 
images params including pitch, width, height and tile mode
for image address caculation

Signed-off-by: Mi, Yanfeng <yanfeng.mi@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:51 +00:00
Lionel Landwerlin
0a42afb262 anv: add a is_sparse for image format support checks 
We'll want to disable some support for software detiled accesses on
sparse 64bit images because we'll pick a single optimized tiling for
shader detiling which is not going to be block shape compliant for
sparse resources.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00
Lionel Landwerlin
5c7397c751 anv: add mapping for VBO formats in format mapping 
We're about to introduce R64_(S|U)INT support for some images. This
will use a different HW format than what we want for VBOs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00
Lionel Landwerlin
eda9422cfc anv: rename compressed format emulation helpers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00
Lionel Landwerlin
ce7208c3ee brw: add support for texel address lowering 
The expectations are :
  - no MSAA images
  - a single tiling mode is used when not linear

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00
Lionel Landwerlin
b25e050ec7 brw: add support for 64bit storage images load/store 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00
Lionel Landwerlin
3bd4c5a166 brw: include UGM fence when TGM + lowered image->global 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00
Lionel Landwerlin
23e14ac41e nir: track lowered image intrinsics to globals 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00
Lionel Landwerlin
38fa9e144c isl: add a helper to report what dimensions a tiling supports 
For shader detiling, it's useful to know if we avoid bothering trying
to detile a 1D image.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00
Lionel Landwerlin
cfa1d40be5 isl: add support for R64 storage image lowering 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00
Lionel Landwerlin
ba03e6734c isl: select a tiling for shader detiling 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676>
 2025-02-23 15:16:50 +00:00