Commit graph

139312 commits

Author SHA1 Message Date
Marek Olšák
87d83f4103 ci: add point coord failures to d3d12
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:56 +00:00
Marek Olšák
5ca7c20cf7 st/mesa: do nir_lower_io() for inputs & outputs with transform feedback info
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:56 +00:00
Marek Olšák
ee4c5b1699 gallium/aux: add helper nir_gather_stream_output_info
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
2a708efec3 gallium/util: add util_dump_stream_output_info
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
1dcd1eac6a nir: pass nir_shader into nir_recompute_io_bases instead of func_impl
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
606811bded nir: add nir_print_xfb_info
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
ad68a1ee5a nir: add nir_gather_xfb_info_from_intrinsics for lowered IO
Drivers will use this.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
d4c051b047 nir: add nir_lower_io_passes() with new transform feedback
moved from radeonsi without the vectorization, which won't be needed for
now. We will lower IO in st/mesa instead of radeonsi to get the transform
feedback info into store instructions.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
3528dcdfa1 nir: add nir_io_semantics::no_varying, no_sysval_output, and helpers
This is for drivers that have separate store instructions for varyings,
system value outputs (such as clip distances), and transform feedback.
The flags tell the driver not to store the output to those locations.

This will be used by radeonsi initially, and then maybe by a new linker.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
548b2d47b2 nir: scalarize transform feedback info in nir_lower_io_to_scalar
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
cc5505088b nir: add shader_info::xfb_strides
NIR now fully contains pipe_stream_output_info in shader_info and IO
intrinsics if lower_io_variables is true. radeonsi will not use
pipe_stream_output_info after this, and other drivers are free to follow
that.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
4636fa7f38 nir: add transform feedback info into nir_intrinsic_store_output
This will allow compaction of transform feedback varyings because they
are no longer tied to varying slots with this information.
It will also make transform feedback info available to all NIR passes
after IO is lowered. It's meant to replace pipe_stream_output_info.

Other intrinsics are not used with transform feedback.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
2c6e41bfe1 nir: fix nir_io_semantics::gs_streams in nir_lower_io_to_scalar
gs_streams is relative to the component. Also clear the high bits.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
73ef225fc2 nir: validate write_mask for all intrinsics that have it
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
2022-03-01 21:59:55 +00:00
Marek Olšák
dd733fa52e radeonsi: fix broken VK-GL buffer interop
Fixes: ad9b5ac0a1 - radeonsi: more fixes for si_buffer_from_winsys_buffer for GL-VK interop
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6063

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15124>
2022-03-01 20:51:04 +00:00
Nanley Chery
c1a7d520f3 anv: Disable aux if the explicit modifier lacks it
For dmabuf imports, configure the primary surface without support for
compression if the modifier doesn't specify it. This helps to create VkImages
with memory requirements that are compatible with the buffers apps provide.

Suggested-by: Philip Langdale <philipl@overt.org>
Cc: 22.0 <mesa-stable>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5940
Tested-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15181>
2022-03-01 20:05:50 +00:00
Nanley Chery
cada519482 anv: Refactor anv_image_init_from_create_info
Use a variable to store the anv_image_create_info struct. We'll modify it for a
bug fix in the next patch.

Cc: 22.0 <mesa-stable>
Tested-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15181>
2022-03-01 20:05:50 +00:00
Nanley Chery
8d2b7e558b anv: Change a parameter of the implicit layout fn
Replace the create_info parameter with isl_extra_usage_flags to more closely
match the parameters of explicit layout function.

Tested-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15181>
2022-03-01 20:05:50 +00:00
Alyssa Rosenzweig
c3eee6327c pan/va: Add missing copyright notice
Minor.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:23 +00:00
Alyssa Rosenzweig
eda00fd39d pan/bi: Extract INSTRUCTION_CASE macro
Useful across multiple optimization tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:23 +00:00
Alyssa Rosenzweig
ffde1f359b pan/bi: Adapt bi_lower_branch for Valhall
Disable the Bifrost optimization; it's not portable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:23 +00:00
Alyssa Rosenzweig
f3937d9874 pan/bi: Trade off registers/threads on Valhall
It's only v6 that's missing this feature.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:23 +00:00
Alyssa Rosenzweig
7637502c8d pan/bi: Add BI_SUBGROUP_SUBGROUP16 option
Valhall uses 16-wide warps.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
ec9c1f8fa6 pan/bi: Wire Valhall disassembler into compiler
Useful when we grow Valhall support (soon!)

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
31e991d801 pan/bi: Support standalone Valhall disassembly
$ bifrost_compiler disasm --gpu=G78 foo.bin

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
600f689a98 pan/bi: Allow CSE of preloaded registers
Needed to CSE `LEA_VARY` in varying shaders on Valhall.

No shader-db changes on Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
3154df232b pan/bi: Use a progress loop for constant folding
Needed to fold the dependent patterns produced by texture instructions
during NIR->Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
e5582710f3 pan/bi: Mark NOP as having no destinations
More accurate and more convenient.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
2604c65174 panfrost: Unify barrier+helper handling
These are unified in the hardware, so let's unify them in pan_shader_info.
Hoisting this logic to pan_shader.c avoids the need to duplicate this logic for
Midgard/Bifrost (RSD packing) and Valhall (SPD packing).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
30d0c2e390 panfrost: Set texel_interleave on Valhall
Instead of specifying the tiling on the texture descriptor, Valhall specifies it
on the plane descriptor. There is a new flag on the texture descriptor
specifying only whether the planes are interleaved or not.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
407bda4d8c panfrost: Adapt estimate_texture_payload_size to Valhall
The plane descriptor is larger than earlier surface descriptors, so we need to
be somewhat careful here. This removes a memory micro-optimization in the
interest of simplifying the code.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
469a36d071 panfrost: Don't emit compression tags on Valhall
Unnecessary. To avoid even more #if/#endif soup, merge the v4, v5-v8, and v9
paths together -- by returning 0 as the compression tag on v4 or v9.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
087b63cb07 panfrost: Allow uploading fragment SPDs
SPDs don't have the state dependence that fragment RSDs do.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
e42b0c68f4 panfrost: Don't pack blend constants with blend shaders
It's probably harmless, but it is logically meaningless. The DDK doesn't do it,
I don't see a reason for us to, either. In theory this should be a small
overhead win.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
111f5af303 panfrost: Generalize some is_bifrost users
Valhall would want these too. Regretting the is_bifrost check at all..

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
36a2b8d039 panfrost: Add PAN_MESA_DEBUG=dump option
To dump all graphics memory via the new pandecode_dump_mappings function(),
since for Valhall I have to do this often enough to warrant a dynamic flag.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
28743a5556 panfrost: Rename prepare_rsd->prepare_shader
This hook will be repurposed on Valhall to prepare the Shader Program
Descriptor, which takes the role of the RSD. Rename to avoid confusion.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
631c01fc42 panfrost: Add an enum for Valhall resource tables
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
f3c971e0fe panfrost: Make Divisor E an integer on v9
For consistency with previous architecture's XML files. Logically this is an
1-bit unsigned integer, not a boolean.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
b19afaf307 panfrost: Clarify contains descriptor? bit
Influences cache prefetching. I don't see a good reason to put anything other
than descriptors inside shader resources, meaning always setting this bit is
appropriate (at least for GLES).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
1df6b0d7e2 panfrost: Remove Invalidate Cache from Valhall job header
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
217e038289 panfrost: Add Tile Render Order enum to fragment jobs
Not sure what this is needed for yet.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Alyssa Rosenzweig
52ccd21e6b panfrost: Extend SPD size
There is software-defined state at the end we don't need. Model in the XML for
correct behaviour.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
2022-03-01 19:43:22 +00:00
Thong Thai
0136545d16 radeonsi: add check for graphics to si_try_normal_clear
Cc: mesa-stable
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15177>
2022-03-01 19:05:06 +00:00
Lionel Landwerlin
214092da87 anv: fix fast clear type value with external images
Disable fast clear if not supported by the external modifier.

v2: Set fast_clear value to NONE in case of import/export from/to external

v3: Move logic next to existing acquire/release checks (Nanley)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6056
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15096>
2022-03-01 17:37:13 +00:00
Oleksandr Gabrylchuk
02fab4cf9e venus: Implement guest vram blob type.
Add support of GUEST_VRAM type of blob. These are dedicated heap memory
allocations required for vk support on hypervisors that don't support
runtime injections of host memory into guest physical address space.

The flow of usage:
1) Host VM reserves dedicated heap memory
2) Device get info about memory reservations and report it to guest
using mmio registers
3) Guest virtio-gpu driver on starts checks mmio registers for
physical address and length of reserved region. Then it reserves it
in guest.
4) On each call of vkAllocateMemory() guest driver gets chunk of
required memory and send it to host using sg list. It uses one sg
entry for 1 blob call. Heap is managed on guest using drm memory
manager (drm_mm).

Signed-off-by: Oleksandr.Gabrylchuk <Oleksandr.Gabrylchuk@opensynergy.com>
Signed-off-by: Andrii Pauk <Andrii.Pauk@opensynergy.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14536>
2022-03-01 17:25:56 +00:00
Marek Olšák
fd3451babd amd: update addrlib
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
2022-03-01 17:03:00 +00:00
Marek Olšák
f8cf5ea982 amd: add support for gfx1036 and gfx1037 chips
Both are identified as GFX1036 for simplicity.

Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
2022-03-01 17:03:00 +00:00
Marek Olšák
48046d5bd8 ac: set correct cache size per TCC for Yellow Carp
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
2022-03-01 17:03:00 +00:00
Samuel Pitoiset
4380916b76 radv: disable DCC for Fable Anniversary, Dragons Dogma, GTA IV and more
Also Starcraft 2 and The Force Unleashed II.

These games are known to be affected by the feedback loop issue. We will
fix this properly soon but as a hotfix disabling DCC should be enough.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4424
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15203>
2022-03-01 16:33:18 +00:00