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Author SHA1 Message Date
Georg Lehmann
859505d95a aco/optimizer: use new helpers to apply literals 
Foz-DB Navi21:
Totals from 21009 (26.33% of 79789) affected shaders:
MaxWaves: 495342 -> 495414 (+0.01%)
Instrs: 22345587 -> 22335371 (-0.05%); split: -0.05%, +0.00%
CodeSize: 122095820 -> 121795112 (-0.25%); split: -0.25%, +0.00%
VGPRs: 1025800 -> 1025480 (-0.03%)
Latency: 202876235 -> 203076272 (+0.10%); split: -0.04%, +0.14%
InvThroughput: 47599930 -> 47596113 (-0.01%); split: -0.03%, +0.02%
VClause: 475271 -> 475439 (+0.04%); split: -0.02%, +0.05%
SClause: 700679 -> 700629 (-0.01%); split: -0.01%, +0.01%
Copies: 1628498 -> 1618165 (-0.63%); split: -0.64%, +0.01%
Branches: 567199 -> 567216 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 952134 -> 952043 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 846614 -> 846272 (-0.04%)
VALU: 15572374 -> 15564050 (-0.05%); split: -0.05%, +0.00%
SALU: 2423329 -> 2421319 (-0.08%); split: -0.08%, +0.00%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

Foz-DB Navi31:
Totals from 13049 (16.44% of 79395) affected shaders:

MaxWaves: 357242 -> 357268 (+0.01%)
Instrs: 19955572 -> 19944106 (-0.06%); split: -0.06%, +0.00%
CodeSize: 105689464 -> 105454348 (-0.22%); split: -0.23%, +0.00%
VGPRs: 765744 -> 764952 (-0.10%); split: -0.11%, +0.00%
Latency: 179063640 -> 179141591 (+0.04%); split: -0.02%, +0.07%
InvThroughput: 27978134 -> 27971318 (-0.02%); split: -0.03%, +0.01%
VClause: 386791 -> 386826 (+0.01%); split: -0.02%, +0.03%
SClause: 598113 -> 598106 (-0.00%); split: -0.01%, +0.01%
Copies: 1393111 -> 1383102 (-0.72%); split: -0.73%, +0.01%
Branches: 498533 -> 498535 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 573310 -> 573236 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 591459 -> 591043 (-0.07%)
VALU: 11623734 -> 11615755 (-0.07%); split: -0.07%, +0.00%
SALU: 1962055 -> 1960005 (-0.10%); split: -0.11%, +0.00%
VOPD: 3544 -> 3566 (+0.62%); split: +0.73%, -0.11%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35272>
 2025-10-14 08:33:39 +00:00
Georg Lehmann
8de89f4ffb aco/optimizer: add alu_opt_info helpers 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35272>
 2025-10-14 08:33:38 +00:00
Georg Lehmann
f436844f39 aco/optimizer: add a new dce helper 
Will be more correct for future constant use cases.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35272>
 2025-10-14 08:33:38 +00:00
Georg Lehmann
0d8219f367 aco/tests: allow even more literals 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35272>
 2025-10-14 08:33:37 +00:00
Samuel Pitoiset
26c7f2fd6a radv: enable the global BO list by default
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vkd3d-proton (DX12) and Zink (GL) have always been enabling features
that require the global BO list to be enabled.

Since DXVK 2.7+ (August 2025), it's also always enabled by default for
DX9-11 games (because it requires BDA now).

The global BO list used to decrease performance in the past mostly
because of bad memory management in AMDGPU, but it seems the situation
slightly improved since. Though, there might still some workloads that
hit the issue, but I think it should be mostly good overall.

This introduces RADV_DEBUG=nobolist to disable the global BO list
when no features require it.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6957
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2331
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35075>
 2025-10-14 08:12:36 +00:00
Samuel Pitoiset
df269714ef radv/meta: remove radv_cmd_buffer_resolve_rendering_{hw,cs,fs} 
Just call the other functions directly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37792>
 2025-10-14 07:46:13 +00:00
Samuel Pitoiset
a81f01bc96 radv/meta: pass iview formats for subpass resolves 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37792>
 2025-10-14 07:46:13 +00:00
Samuel Pitoiset
d3e716f1fb radv/meta: re-use radv_meta_resolve_{fragment,hardware}_image() for subpass resolves 
Similar to compute.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37792>
 2025-10-14 07:46:13 +00:00
Samuel Pitoiset
ac3c21f130 radv/meta: pass image formats to radv_meta_resolve_{hardware,fragment}_image() 
Similar to the compute function.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37792>
 2025-10-14 07:46:12 +00:00
Samuel Pitoiset
e982f6e2c8 radv: fix shaders memleak when importing pipeline binaries with GPL 
The implementation must use the data in VkPipelineBinaryInfoKHR when
provided instead of importing binaries from libraries.

This fixes a memleak with shaders found with ASAN.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37844>
 2025-10-14 06:54:02 +00:00
Samuel Pitoiset
876e6a3bfe radv/rt: fix memory leak in lower_rt_instructions_monolithic() 
Found with ASAN.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37844>
 2025-10-14 06:54:02 +00:00
Georg Lehmann
e26a8be7af ac/nir: enable nir atomic load/store opts 
Foz-DB GFX1201:
Totals from 4 (0.00% of 80287) affected shaders:
Instrs: 2928 -> 2920 (-0.27%); split: -0.31%, +0.03%
CodeSize: 15424 -> 15392 (-0.21%); split: -0.23%, +0.03%
Latency: 835578 -> 823220 (-1.48%)
InvThroughput: 3307941 -> 3258515 (-1.49%)
Copies: 459 -> 447 (-2.61%)
VALU: 1297 -> 1291 (-0.46%)
SALU: 595 -> 589 (-1.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37822>
 2025-10-14 06:24:17 +00:00
Georg Lehmann
6eac72088c aco/gfx10+: only work around split execution of uniform LDS in WGP mode
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LDS instructions from one CU won't split the execution of other LDS instruction
on the same CU.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31630>
 2025-10-13 10:22:22 +00:00
Georg Lehmann
c13caa5e5f aco: fix global_atomic_swap offset overflow check 
Fixes: d7dcd81c77 ("aco/gfx6: allow both constant and gpr offset for global with sgpr address")

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37821>
 2025-10-13 09:41:41 +00:00
Emma Anholt
f7cbc7b1c5 radv: Allocate BOs as implicit sync even if the WSI is doing implicit sync. 
As noted, the flag we allocate with controls whether *anyone* can implicit
sync on the BO through amdgpu interfaces, not just whether our fd does.
This restores radv to the behavior before the regressing commit.

Fixes: 4dcf32c56e ("wsi/drm: Don't request implicit sync if we're doing implicit sync ourselves.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37772>
 2025-10-10 19:17:04 +00:00
Emma Anholt
38ac55ebff radv: Restore marking WSI image's mem->buffer as uncached. 
Prior to 4dcf32c56e, radv was getting a request for implicit sync, even
when we were doing the work to do implicit sync in the WSI.  Once that was
turned off, we incidentally dropped flagging WSI's mem->buffer as
uncached, due to it being under the wrong condition.

Fixes: 4dcf32c56e ("wsi/drm: Don't request implicit sync if we're doing implicit sync ourselves.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37772>
 2025-10-10 19:17:04 +00:00
Hans-Kristian Arntzen
2848901722 radv: Actually fail custom border color sampler creation. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: a52483d9e7 ("radv: fix capture/replay with sampler border color")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37787>
 2025-10-10 14:25:54 +00:00
Samuel Pitoiset
183ed8046c radv: allow VK_FORMAT_S8_UINT with host image copy 
Depth/stencil formats still need to be properly implemented.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37748>
 2025-10-10 13:46:51 +00:00
Samuel Pitoiset
ef900e93fc ac/surface: fix host image copies with stencil-only 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37748>
 2025-10-10 13:46:51 +00:00
Samuel Pitoiset
9a7f1401d8 ac/surface: fix host image copies with 96-bits formats 
Fixes dEQP-VK.image.host_image_copy.simple.r32g32b32_* with
RADV_PERFTEST=hic on RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37748>
 2025-10-10 13:46:51 +00:00
Samuel Pitoiset
d063072182 radv: rename radv_mark_descriptor_sets_dirty()
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Descriptor heaps will be marked as dirty in this function too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:05 +00:00
Samuel Pitoiset
34b3dae3b6 radv: make radv_descriptor_get_va() a static function 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:05 +00:00
Samuel Pitoiset
08dbab0600 radv: rename shader arg descriptor_sets to descriptors 
It's more generic and descriptor heaps will use it too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:03 +00:00
Samuel Pitoiset
609ae4e647 radv: rename indirect_descriptor_sets to indirect_descriptors 
With descriptor heap the driver will also have to emit indirect
descriptor heaps in some cases.

Rename couple of things to make them more generic.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:03 +00:00
Samuel Pitoiset
0ff1ce4ac5 radv: use force_indirect_desc_sets when creating RT prologs 
This is cleaner and this field has been added exactly for that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:02 +00:00
Samuel Pitoiset
055b10a75c radv: do not initialize HiZ on transfer queue on RDNA4 
Emitting compute dispatches on SDMA would just hang.

This fixes pending depth/stencil copy tests on transfer queue with
RADV_PERFTEST=transfer_queue.

Fixes: e6c485afb0 ("radv: initialize HiZ metadata during image layout transitions")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37795>
 2025-10-10 12:50:02 +00:00
Samuel Pitoiset
aeec53f020 radv,radeonsi: use new ac_cmdbuf macros 
But keep them behind existing macros for consistency until all macros
are moved to common code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:15 +00:00
Samuel Pitoiset
902f5a8618 radv: replace radeon_cmdbuf by ac_cmdbuf completely 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:15 +00:00
Samuel Pitoiset
9ff4750eaf ac/cmdbuf: introduce ac_cmdbuf 
This will be shared by both drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:14 +00:00
Samuel Pitoiset
a7ae26c96c ac/sqtt: use void pointers for start/stop CS 
Similar to BOs which are different structs between drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:14 +00:00
Samuel Pitoiset
12cccb2f75 radv: remove useless radeon_cmdbuf forwarded declaration 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:13 +00:00
Rhys Perry
c63c695149 radv: move nir_opt_algebraic loop for NGG culling earlier
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Details 
Totals from 6913 (8.66% of 79825) affected shaders: (Navi21)
Instrs: 5373319 -> 5358717 (-0.27%); split: -0.30%, +0.03%
CodeSize: 27448536 -> 27345464 (-0.38%); split: -0.41%, +0.03%
SpillSGPRs: 982 -> 998 (+1.63%)
Latency: 22998827 -> 23011602 (+0.06%); split: -0.13%, +0.19%
InvThroughput: 4663749 -> 4664809 (+0.02%); split: -0.00%, +0.03%
VClause: 120845 -> 120461 (-0.32%); split: -0.49%, +0.17%
SClause: 119068 -> 116064 (-2.52%); split: -2.71%, +0.18%
Copies: 456590 -> 456450 (-0.03%); split: -0.19%, +0.16%
Branches: 145555 -> 145559 (+0.00%); split: -0.00%, +0.01%
PreSGPRs: 300465 -> 301154 (+0.23%); split: -0.01%, +0.24%
VALU: 3064127 -> 3064210 (+0.00%); split: -0.00%, +0.00%
SALU: 891257 -> 886368 (-0.55%); split: -0.71%, +0.16%
SMEM: 190500 -> 184624 (-3.08%); split: -3.11%, +0.02%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:54:11 +00:00
Marek Olšák
3fe651f607 nir: remove load_smem_amd 
replaced by load_global_amd + ACCESS_SMEM_AMD

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:54:11 +00:00
Daniel Schürmann
3ae2f12eb4 ac/nir: switch load_smem_amd to use load_global 
Totals from 24920 (31.21% of 79839) affected shaders: (Navi48)

Instrs: 22044185 -> 22413945 (+1.68%); split: -0.01%, +1.68%
CodeSize: 117211728 -> 118623656 (+1.20%); split: -0.01%, +1.21%
VGPRs: 1199008 -> 1198948 (-0.01%)
SpillSGPRs: 7421 -> 7365 (-0.75%); split: -0.78%, +0.03%
SpillVGPRs: 2177 -> 2184 (+0.32%); split: -0.09%, +0.41%
Scratch: 7037952 -> 7038208 (+0.00%)
Latency: 155140452 -> 155530877 (+0.25%); split: -0.02%, +0.27%
InvThroughput: 23601713 -> 23634131 (+0.14%); split: -0.01%, +0.15%
VClause: 458456 -> 458575 (+0.03%); split: -0.09%, +0.11%
SClause: 651928 -> 649405 (-0.39%); split: -1.26%, +0.87%
Copies: 1681110 -> 1677057 (-0.24%); split: -0.42%, +0.17%
Branches: 515419 -> 515322 (-0.02%); split: -0.02%, +0.00%
PreSGPRs: 992903 -> 990545 (-0.24%); split: -0.24%, +0.00%
VALU: 11971995 -> 11967962 (-0.03%); split: -0.04%, +0.00%
SALU: 3247576 -> 3476720 (+7.06%); split: -0.03%, +7.08%
VMEM: 821046 -> 821056 (+0.00%); split: -0.00%, +0.00%
SMEM: 988476 -> 988779 (+0.03%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:54:11 +00:00
Daniel Schürmann
2622a3bc47 radv,radeonsi: call ac_nir_lower_global_access and nir_lower_int64 for gs copy shaders 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:54:08 +00:00
Daniel Schürmann
50fcfe6bd8 radv: delay nir_opt_shrink_vectors 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:54:05 +00:00
Daniel Schürmann
fdd6bdf03d ac/nir_lower_global_access: don't assume pack_64_2x32 is the same as u2u64 
It might also be the expanded base address.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:53:58 +00:00
Daniel Schürmann
0209065229 ac/nir_lower_global_access: require no_unsigned wrap when extracting from 32-bit additions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:53:58 +00:00
Daniel Schürmann
c82d70d3ec radv: delay lowering int64 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:53:53 +00:00
Daniel Schürmann
eda8fc1e90 radv: delay lowering global access 
Totals from 21 (0.03% of 79839) affected shaders: (Navi48)

Instrs: 30258 -> 30249 (-0.03%); split: -0.05%, +0.02%
CodeSize: 159660 -> 159552 (-0.07%); split: -0.07%, +0.01%
Latency: 188154 -> 188131 (-0.01%); split: -0.02%, +0.00%
SClause: 251 -> 252 (+0.40%)
SMEM: 619 -> 598 (-3.39%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:53:53 +00:00
Rhys Perry
20af16b4d8 aco: use MTBUF for 64-bit atomic load/store
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A 64-bit atomic load/store should be considered entirely out-of-bounds if
any part of it is out-of-bounds. Since we implemented these as 32-bit vec2
load/store, it would have been possible for the first half to be in-bounds
while the second half is out-of-bounds.

From 9.6.1. Robust Buffer Access of Vulkan 1.4.324 specification:
> Any non-atomic access to a uniform, storage, uniform texel, or storage
> texel buffer wider than 32-bits may be treated as multiple 32-bit
> accesses that are separately bounds checked.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36602>
 2025-10-07 17:41:31 +00:00
Rhys Perry
f905acfada aco: remove barrier acquire/release workaround 
This existed since ccfe9813fb because NIR
had no atomic loads/stores. This is no longer the case.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36602>
 2025-10-07 17:41:31 +00:00
Rhys Perry
271b135b03 aco: set atomic semantic for atomic load/store 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36602>
 2025-10-07 17:41:30 +00:00
Rhys Perry
74b807cf58 aco: only workaround load tearing for atomic loads 
For non-atomic loads, this situation would require a data race.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36602>
 2025-10-07 17:41:30 +00:00
Timur Kristóf
c473b0b551 radv/amdgpu: Allow IB2 when primary CS isn't chained
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The primary CS doesn't need to use chaining in order to use IB2.
Allow using IB2 packets when chaining is disabled.

Rationale for this patch:
When chaining is enabled (the default), this patch removes a
useless check.
When chaining is disabled (by noibchaining), this patch allows us
to use IB2 without chaining.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37280>
 2025-10-07 15:49:02 +00:00
Timur Kristóf
503963c08c radv/amdgpu: Support IB2 without chaining, enable on GFX6 
GFX6 supports IB2 but not chaining within an IB2.

To use IB2 on GFX6, disable chaining in secondary CS,
and emit an IB2 packet for each secondary IB.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37280>
 2025-10-07 15:49:02 +00:00
Timur Kristóf
92ba76710d ac/gpu_info: Add can_chain_ib2 field to ac_gpu_info 
GFX6 supports IB2, but not chaining inside IB2.
It only supports chaining in IB1.
See waCpIb2ChainingUnsupported in PAL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37280>
 2025-10-07 15:49:01 +00:00
Timur Kristóf
2091db2461 radv/amdgpu: Small cleanup of counting submitted IBs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37280>
 2025-10-07 15:49:01 +00:00
Timur Kristóf
fd5c50664e radv/amdgpu: Emit a single 4 dword NOP in chainable CS buffers 
This is a small optimization that should slightly reduce the CP
overhead for all GPUs as we now only emit a single NOP packet
instead of 4.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37280>
 2025-10-07 15:49:01 +00:00
Timur Kristóf
e6a1355bd5 radv/amdgpu: Add a helper function to emit NOP packets 
No functional changes, just make the code a bit easier to read.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37280>
 2025-10-07 15:49:00 +00:00