Commit graph

31017 commits

Author SHA1 Message Date
George Kyriazis
909f72e0a2 swr: fix polygonmode for front==back
Rasterizer core only supports polygonmode front==back.  Add logic for
populating fillMode for the rasterizer only for that case correctly.
Provide enum conversion between mesa enums and core enums.

The core renders lines/points as tris. Previously, code would enable
stipple for polygonmode != FILL.  Modify stipple enable logic so that
this works correctly.

No regressions in vtk tests.
Fixes the following piglit tests:
	pointsprite
	gl-1.0-edgeflag-const

v2: remove cc stable, and remove "not implemented" assert
v3: modified commit message

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-08 21:28:53 -05:00
George Kyriazis
26a9ed6f0f swr/rast: support polygonmode point
Add support for polygonmode point in the binner.  This is done by
splitting BinPostSetupPoints from BinPoints, so the earlier call can be
called from BinTriangles.  Setup has already been done at the time
BinPostSetupPoints needs to be called.

This checkin just adds support in the rasterizer.  A separate checkin
will add the appropriate driver support.

v2: remove cc stable
v3: modified commit message and subject line

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-08 21:28:53 -05:00
Timothy Arceri
34c5e58a68 util: move ALWAYS_INLINE macro to util/macro.h
Also added clang check.

macro.h is include by p_compiler.h so no other change is needed.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-09 11:21:03 +10:00
Bruce Cherniak
f52e63069a swr: move msaa resolve to generalized StoreTile
v3: list piglit tests fixed by this patch. Fixed typo Tim pointed out.
v2: Reword commit message to more closely adhere to community
guidelines.

This patch moves msaa resolve down into core/StoreTiles where the
surface format conversion routines are available.  The previous
"experimental" resolve was limited to 8-bit unsigned render targets.

This fixes a number of piglit msaa tests by adding resolve support for
all the render target formats we support.

Specifically:
layered-rendering/gl-layer-render: fail->pass
layered-rendering/gl-layer-render-storage: fail->pass
multisample-formats *[2,4,8,16] gl_arb_texture_rg: crash->pass
multisample-formats *[2,4,8,16] gl_ext_texture_snorm: crash->pass
multisample-formats *[2,4,8,16] gl_arb_texture_float: fail->pass
multisample-formats *[2,4,8,16] gl_arb_texture_rg-float: fail->pass

MSAA is still disabled by default, but can be enabled with
"export SWR_MSAA_MAX_COUNT=4" (1,2,4,8,16 are options)
The default is 0, which is disabled.

This patch improves the number of multisample-formats supported by swr,
and fixes several crashes currently in the 17.1 branch.  Therefore, it
should be considered for inclusion in the 17.1 stable release.  Being
disabled by default, it poses no risk to most users of swr.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
cc: mesa-stable@lists.freedesktop.org
2017-05-08 14:45:40 -05:00
Marek Olšák
25d246f454 radeonsi: rename si_eliminate_const_vs_outputs -> si_optimize_vs_outputs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-08 19:18:29 +02:00
Nicolai Hähnle
cb2ac69628 radeonsi: split per-patch from per-vertex indices
Make it a bit clearer that the index spaces are logically seperate by
having them defined in different functions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-08 17:42:17 +02:00
Nicolai Hähnle
707df19451 radeonsi: clarify documentation of existing SI workaround
Limiting LS-HS to a single wave is required on all SI chips due to an
issue with a power management feature.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-08 17:42:17 +02:00
Nicolai Hähnle
f16b755863 radeonsi: fix gl_PrimitiveID in tessellation with instanced draws on SI
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-08 17:42:17 +02:00
Nicolai Hähnle
b84b631c63 radeonsi: load patch_id for TES-as-ES when exporting for PS
For some reason, this change is only necessary on SI.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-08 17:42:17 +02:00
Nicolai Hähnle
0549ea15ec radeonsi: fix primitive ID in fragment shader when using tessellation
In a VS->TCS->TES->PS pipeline, the primitive ID is read from TES exports,
so it is as if TES were using the primitive ID.

Specifically, this fixes a bug where the primitive ID is not reset at
the start of a new instance.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-08 17:42:17 +02:00
Nicolai Hähnle
854ed47f3e radeonsi: mark fast-cleared textures as compressed when dirtying
There are a bunch of piglit fast clear tests that regressed on SI, for
example ./bin/ext_framebuffer_multisample-fast-clear single-sample.

The problem is that a texture is bound as a framebuffer, cleared, and
then rendered from in a loop that loops through different clear colors.
The texture is never rebound during all this, so the change to
tex->dirty_level_mask during fast clear was not taken into account
when checking for compressed textures.

I have considered simply reverting the problematic commit. However,
I think this solution is better. It does require looping through all
bound textures after a fast clear, but the alternative would require
visiting more textures needless on every draw. Draws are much more
common than clears.

Note that the rendering feedback loop rules do not apply here, because
the framebuffer binding is changed between the glClear and the draw
that samples from the texture that was cleared.

Fixes: bdd6449769 ("radeonsi: don't mark non-dirty textures with CMASK as compressed")
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-08 17:42:16 +02:00
Pierre Moreau
27ad060c6e nv50/ir: Replace NV50_PROGRAM_IR_* by PIPE_SHADER_IR_*
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-05-07 10:26:37 -04:00
Pierre Moreau
8fe5949b08 nv50/ir: Remove unused translation methods
This code was merged commented out, and has stayed that way ever since.

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-05-07 10:26:36 -04:00
Pierre Moreau
dd7ab4dcb4 nv50/ir: Free target if we failed to create a program
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-05-07 10:26:36 -04:00
Pierre Moreau
b490ca9a38 nv50/ir: Fail if encountering unknown shader type
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-05-07 10:26:36 -04:00
Marek Olšák
314657dc11 Revert "radeonsi: constify a bunch of the perfcounter structs."
This reverts commit 7088b655e8.

It breaks performance counters. If you use them with this commit, they hang
the machine hard. Sysrq and ssh don't work.
2017-05-06 21:17:52 +02:00
Marek Olšák
b0d01bd303 Revert "radeonsi: fix build with GCC 4.8"
This reverts commit 485ece83ac.

It's needed to revert 7088b655e8.
2017-05-06 21:17:52 +02:00
Rob Clark
6050d5bf3d freedreno/a3xx: fix hang w/ large render targets and small gmem
Possibly other gen's have a similar limit.  Fixes glmark2 -b shadow
with larger resolutions on devices with small gmem (for example,
fullscreen 1080p on 8x16/db410c).

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-06 14:16:33 -04:00
Rob Clark
4fadfbf176 freedreno/ir3: add macro to declare variable length arrays
We have enough of these, that we should stop open coding this.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-06 14:15:42 -04:00
Marek Olšák
ee5908396e radeonsi: apply the tess+GS hang workaround to Polaris12 as well
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 18:55:03 +02:00
Samuel Pitoiset
485ece83ac radeonsi: fix build with GCC 4.8
Fixes: 7088b655e8 ("radeonsi: constify a bunch of the perfcounter structs.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100937
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-05 18:29:30 +02:00
Marek Olšák
69e6eab653 winsys/amdgpu: fix Polaris12 (RX 550) breakage
reported by Greg White.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100892
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
2017-05-05 01:21:32 +02:00
Marek Olšák
194d9b27cc radeonsi/gfx9: allow the scratch buffer in HS and GS
It works now.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
8ac4923a67 radeonsi: prevent race conditions when doing scratch patching
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
9dfc030b48 radeonsi: separate scratch state patching code into its own function
Picked from a different branch. When we stop using the scratch patching,
this function will not be called.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
1b01014cbf radeonsi/gfx9: also apply scratch relocations to the 1st shader of merged shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
e107c5a426 radeonsi/gfx9: set correct LLVM calling conventions for merged shaders
for scratch support

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
a47289f8fc radeonsi: remove unused parameters from si_shader_apply_scratch_relocs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
2d662c0cba radeonsi: inline si_llvm_shader_type into si_llvm_create_func
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
4c0e68dfe5 radeonsi: don't use util_memcpy_cpu_to_le32 for shader uploads
at least I think this is correct.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
7660c9ee4e radeonsi: make si_compile_llvm static
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
f8f8242e8b radeonsi: fold surrounding code into si_llvm_finalize_module
and rename to si_llvm_optimize_module.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
5dad0c3477 radeonsi: don't call eliminate_const_vs_outputs in shaders without VS exports
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
12beef0374 radeonsi: drop support for LLVM 3.8
LLVM 3.8:
- had broken indirect resource indexing
- didn't have scratch coalescing
- was the last user of problematic v16i8
- only supported OpenGL 4.1

This leaves us with LLVM 3.9 and LLVM 4.0 support for Mesa 17.2.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
4d32b4ac99 radeonsi: stop using v16i8
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Marek Olšák
283a1d1e27 radeonsi/gfx9: make some PA & DB registers match the closed Vulkan driver
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-05 00:23:44 +02:00
Rob Clark
7b55a05159 freedreno/a5xx: compute shader support
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-04 13:48:06 -04:00
Rob Clark
10c17f23b7 freedreno: core compute state support
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-04 13:48:06 -04:00
Rob Clark
2ce449fa7d freedreno/ir3: compute shader support
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-04 13:48:06 -04:00
Rob Clark
39c5a46a7a freedreno/a5xx: SSBO support
To simplify things for now, since all the gfx shader stages share a
single SSBO state block, only advertise SSBO support for fragment shader
(and compute when we have that).  We could possibly use a fixed-
partitioning of the SSBO index space to support SSBOs on other stages
without having to resort to shader variants.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-04 13:48:06 -04:00
Rob Clark
edde00f5f1 freedreno/ir3: SSBO/atomic support
TODO cwabbott pointed out a write-after-read hazzard, which effects both
this and arrays.  A write needs to depend on *all* reads since the last
write, not just the last read.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-04 13:48:06 -04:00
Rob Clark
4d841fbaae freedreno: core SSBO support
The generation-independent support for binding shader buffer objects.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-04 13:48:06 -04:00
Rob Clark
fd6ed7b562 freedreno/ir3: resync instr-a3xx.h/disasm-a3xx.c
Sync to the same files from freedreno.git to correct decoding of ldgb/
stgb instructions.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-04 13:48:06 -04:00
Emil Velikov
4752ae876a targets/libgl-xlib: remove unneeded GLX_SHARED_GLAPI define
There's no users in-tree that use it.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-04 18:11:56 +01:00
Emil Velikov
4ea5f4b74c gallium/dri: remove unneeded HAVE_SHARED_GLAPI guard
Always true, since the dri modules required shared glapi.

With earlier commit (da410e6afa "configure: explicitly require shared
glapi for enable-dri") we even made that explicit during the configure
stage.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-04 18:11:40 +01:00
Emil Velikov
79a26b663a gallium/dri: always link against shared glapi
In the early days of Xorg and Mesa we had multiple providers of the
GLAPI. All of those were the ones responsible for dlopening the DRI
module. Hence it was perfectly fine, and actually expected, for the DRI
modules to have unresolved symbols.

Since then we've moved the API to a separate shared library and no other
libraries provide the symbols.

Here comes the picky part:
It's possible that one uses old Xorg (where libglx.so provides the
GLAPI) and new Mesa (with DRI modules linking against libglapi.so).

That should still work, since the the libglx.so symbols will take
precedence over the libglapi.so ones.

I've verified this while running 1.14 series Xorg alongside this (and
next) patch.

It may seem a bit fragile, but that's of reasonably OK since all of the
affected Xorg versions have been EOL for years.

The final one being the 1.14 series, which saw its final bug fix release
1.14.7 in June 2014.

To ensure that the binaries do not have unresolved symbols add
-no-undefined and $(LD_NO_UNDEFINED), just like we do everywhere else
throughout mesa.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98428
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-04 18:11:29 +01:00
Dave Airlie
7088b655e8 radeonsi: constify a bunch of the perfcounter structs.
This moves the structs from the data segment to the rodata segment,
which seems like the more correct place for them.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-05-04 11:52:47 +10:00
Marek Olšák
f466683cb0 radeonsi/gfx9: fix gl_ViewportIndex
v2: remove unnecessary LLVMBuildAnd calls

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-03 22:58:27 +02:00
Marek Olšák
ec34632859 radeonsi/gfx9: set VGT_REUSE_OFF = 0
same as Vulkan

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-03 22:58:27 +02:00
Christian Gmeiner
a8007ed687 etnaviv: add L8A8_UNORM texture format
No piglit regressions.

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-05-03 22:43:10 +02:00