Commit graph

1858 commits

Author SHA1 Message Date
Timothy Arceri
82adf53308 ac: image size builtin for GLSL_SAMPLER_DIM_3D
This is what radeonsi does. Fixes remaing piglit subtest in:

./bin/arb_shader_image_size-builtin --quick -auto -fbo

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 18:05:13 +11:00
Timothy Arceri
5b9362c248 ac: fix ac_build_varying_gather_values() for packed layouts
This fixes a segfault for varyings not starting at component 0.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 10:00:52 +11:00
Timothy Arceri
209b14c2cb ac: remove arrays when when querying sampler info
Fixes the following ARB_arrays_of_arrays piglit tests:

basic-imagestore-const-uniform-index
basic-imagestore-mixed-const-non-const-uniform-index
basic-imagestore-mixed-const-non-const-uniform-index2
basic-imagestore-non-const-uniform-index

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 09:50:47 +11:00
Timothy Arceri
324d2fe6a7 ac: fix emit vertex stream parameter
Fixes the following piglit test on radeonsi:

./bin/arb_enhanced_layouts-gs-stream-location-aliasing

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 09:30:00 +11:00
Timothy Arceri
271067967a ac: add support for gl_HelperInvocation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 09:23:26 +11:00
Timothy Arceri
3bc5fa69f5 ac/radeonsi: add emit primitive to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 09:18:37 +11:00
Timothy Arceri
fdc2fb4d88 ac: add stream handling to visit_end_primitive()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 09:18:36 +11:00
Timothy Arceri
882af004d8 ac/nir/radeonsi: add ARB_shader_ballot support
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 09:11:22 +11:00
Timothy Arceri
4a9643413f ac/nir: add ARB_shader_group_vote support
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-23 09:11:22 +11:00
Samuel Pitoiset
33e6e5e6a4 radv: add an option that allows to dump pre-optimization ir
With RADV_DEBUG=preoptir.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-22 12:28:33 +01:00
Matthew Nicholls
005375717b radv: restore previous stencil reference after depth-stencil clear
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alex Smith <asmith@feralinteractive.com>
2018-01-22 08:57:42 +00:00
Bas Nieuwenhuizen
4584c4ef04 radv: Don't allow 3d or 1d depth/stencil textures.
addrlib asserts when that happens, and supporting it is not
required so lets not allow this for now.

It also assert on fmask, but we don't have the number of samples here.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:43 +01:00
Bas Nieuwenhuizen
8b98929074 radv: Init variant entry with memset.
This gets memcpy'd and written driectly, and due to alignment, this
resulted in uninitialized gaps. This makes those gaps go away.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:39 +01:00
Bas Nieuwenhuizen
fb0992e967 radv: Fix bufimage failure deallocation.
The inidividual init parts don't clean up their own stuff on failure.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:32 +01:00
Bas Nieuwenhuizen
2c802ca66c radv: Fix fragment resolve init memory allocation failure paths.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:29 +01:00
Bas Nieuwenhuizen
c685076ab0 radv: Fix freeing meta state if the device pipeline cache fails to allocate.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:24 +01:00
Bas Nieuwenhuizen
71f0315a88 radv: Fix memory allocation failure path in compute resolve init.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:19 +01:00
Bas Nieuwenhuizen
d956e0bdf5 radv: Fix ordering issue in meta memory allocation failure path.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:03 +01:00
Dylan Baker
436ed65d38 autotools: include meson build files in tarball
This adds the meson.build, meson_options.txt, and a few scripts that are
used exclusively by the meson build.

v2: - Remove accidentally included changes needed to test make dist with
      LLVM > 3.9

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 16:30:51 -08:00
Bas Nieuwenhuizen
61a790409e radv: Always re-emit the sample position offset user SGPR.
The user SGPR location can change between pipelines, so we need to
emit it again to the pottentially changed SGPR index.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 23:35:12 +01:00
Bas Nieuwenhuizen
dbf1e918cd radv: emit pa_sc_mode_cntl_0 with multisample state.
We don't have the meta kludge with 0 viewports anymore,
so we can always enable them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 23:35:12 +01:00
Bas Nieuwenhuizen
32170d87e3 ac/nir: Fix vector extraction if source vector has >4 elements.
v2: Add forgotten argument and start offset.

Fixes: 91074bb11b "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-19 02:00:28 +01:00
Bas Nieuwenhuizen
f4211e6f93 ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.
Fixes: 91074bb11b "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-19 02:00:14 +01:00
Bas Nieuwenhuizen
4a9fd90e1e ac/nir: Fix TCS output LDS offsets.
When a channel was not set we also did not increase the LDS address,
while that obviously should happen.

The output loading code was inadvertently fixed which resulted in a
mismatch causing the SaschaWillems tessellation demo to result
in corrupt rendering.

Fixes: 7898eb9a60 "ac: rework load_tcs_{inputs,outputs}"
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-19 01:54:59 +01:00
Bas Nieuwenhuizen
bd5c942cef radv: Use correct bindings for inputRate in key generation.
The bindings also have an index field.

Fixes: 49d035122e "radv: Add single pipeline cache key."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104677
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 01:54:59 +01:00
Bas Nieuwenhuizen
b1444c9ccb radv: Implement VK_ANDROID_native_buffer.
Passes
  dEQP-VK.api.smoke.*
  dEQP-VK.wsi.android.*

with android-cts-7.1_r12 .

Unlike the initial anv implementation this does
use syncobjs instead of waiting on the CPU.

This is missing meson build coverage for now.

One possible todo is that linux 4.15 now has a
sycall that allows us to export amdgpu fence to
a sync_file, which allows us not to force all
fences and semaphores to use syncobjs. However,
I had trouble with my kernel crashing regularly
with NULL pointers, and I'm not sure how beneficial
it is in the first place given that intel uses
syncobjs for all fences if available.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-19 01:43:55 +01:00
Bas Nieuwenhuizen
a3e241ed07 radv: Add create image flag to not use DCC/CMASK.
If we import an image, we might not have space in the
buffer for CMASK, even though it is compatible.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-19 01:43:55 +01:00
Bas Nieuwenhuizen
e344cd8178 radv: Generate VK_ANDROID_native_buffer.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-19 01:43:55 +01:00
Bas Nieuwenhuizen
0f89f9b8eb radv: Replace an assert with unreachable.
Otherwise we get uninitialized variable warnings for es_vgpr_comp_cnt.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 00:38:45 +01:00
Bas Nieuwenhuizen
e417ab212b radv: Remove DCC check on CS resolve dst image.
Gives a warning when the assert is disabled, and not even
necessarily true.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 00:38:45 +01:00
Timothy Arceri
3bccb5dba9 ac: fix visit_ssa_undef() for doubles
V2: use LLVMIntTypeInContext()

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-19 08:09:04 +11:00
Dave Airlie
3153d74207 ac/nir: account for view index in the user sgpr allocation.
The view index user sgpr wasn't being accounted for properly,
this refactors out the code to decide if it's required and then
uses that info to account for it.

Fixes: 180c1b924e (ac/nir: Add shader support for multiviews.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 19:47:40 +00:00
Timothy Arceri
9248f72c4e ac: tidy up array indexing logic
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-18 15:59:27 +11:00
Dave Airlie
6785034a70 radv/ws: get rid of useless return value
This also used boolean, so nice to kill that.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 01:57:53 +00:00
Bas Nieuwenhuizen
2ce11ac11f radv: Initialize DCC on transition from preinitialized.
Looks like the decompress does not handle invalid encodings well,
which happens with random memory. Of course apps should not use it
with random memory, but they are allowed to ....

Fixes: 44fcf58744 "radv: Disable DCC for GENERAL layout and compute transfer dest."
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-18 01:57:52 +01:00
Timothy Arceri
e2b9296146 ac: fix buffer overflow bug in 64bit SSBO loads
Fixes: 441ee1e65b "radv/ac: Implement Float64 SSBO loads"

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-18 10:26:58 +11:00
Timothy Arceri
409e15f26f ac: fix nir_intrinsic_get_buffer_size for radeonsi
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-18 10:25:20 +11:00
Timothy Arceri
7898eb9a60 ac: rework load_tcs_{inputs,outputs}
This shares more code and calls the new shared load_tess_varyings()
abi so that the radeonsi nir path now supports tcs output loads.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-18 00:03:33 +11:00
Timothy Arceri
9622b445c8 ac/radeonsi: add tcs load outputs support
The code to load outputs is essentially the same as load inputs
so we make the interface more generic to maximise code sharing.

We will make use of the new support in the following patch.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-18 00:03:33 +11:00
Bas Nieuwenhuizen
0b8991c0b6 radv: Implement VK_EXT_debug_report.
This is not hooked up to any messages yet, but useful for e.g.
renderdoc if you add some messages during development.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-17 11:29:04 +01:00
Samuel Pitoiset
05f73b9672 ac: set no-signed-zeros-fp-math when RADV_DEBUG="unsafemath" is used
This is an optimisation that is recommended by Matt Arsenault,
and used by RadeonSI, but it's not compatible with Vulkan.

Note that AC_FLOAT_MODE_UNSAFE_FP_MATH includes the no signed
zeros flag in LLVM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-16 21:39:57 +01:00
Samuel Pitoiset
4f5318df2c ac: set fast math flags when RADV_DEBUG="unsafemath" is used
When that debug option is not used, we use the default float mode
because the no signed zeros optimisation is not Vulkan compatible.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-16 21:39:55 +01:00
Samuel Pitoiset
2091206ad3 ac: import lp_create_builder() from gallivm
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-16 21:39:53 +01:00
Samuel Pitoiset
ad2b3b2a9c ac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6
This also replaces llvm.AMDGPU.kilp by llvm.AMDGPU.kill with
LLVM < 6. Similar to RadeonSI codepath.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-16 21:39:51 +01:00
Samuel Pitoiset
8045f01e2a Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"
This can't work for two reasons:
- TESSINNER/TESSOUTER are shader input values, so never translated
to the intrinsic ops
- the shader info pass scans the current stage but we want to know
in TCS, if TES reads the tess factors.

This fixes 6 regressions related to
deqp-vk/tessellation/shader_input_output/tess_level_{inner,outer}_XXX_tes

This reverts commit 5ba1a61648.
2018-01-15 13:47:18 +01:00
Samuel Pitoiset
5842cb0df1 amd/common: fix loading InstanceID for tess on < GFX9
InstanceID is in VGPR2, not 1.

One more failure that CTS didn't catch up...

Reported-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-15 11:59:16 +01:00
Samuel Pitoiset
5ba1a61648 ac/shader: gather If TES reads TESSINNER or TESSOUTER
This shouldn't be scanned in the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-15 11:51:47 +01:00
Samuel Pitoiset
aebde47840 ac: remove ac_shader_variant_info::fs::output_mask
Unused.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-15 11:48:42 +01:00
Timothy Arceri
e6378962ce ac: add doubles support to isign
Fixes a number of int64 piglit tests, for example:

generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-14 11:40:03 +11:00
Timothy Arceri
38876c88d1 ac: add i64_0 and i64_1 to llvm build context
These will be used in the following patch.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-14 11:40:03 +11:00