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37 commits

Author SHA1 Message Date
Chia-I Wu
81d7f33e30 ilo: move away from drm_intel_bo_alloc_tiled 
We want to know the exact sizes of the BOs, and the driver has the knowledge
to do so.  Refactoring of the resource allocation code is needed though.
 2014-07-15 12:00:10 +08:00
Chia-I Wu
3e324f99d3 ilo: replace bo alloc flags by initial domains 
The only alloc flag is INTEL_ALLOC_FOR_RENDER, which can as well be expressed
by specifying the initial write domain.  The change makes it obvious that we
failed to set INTEL_ALLOC_FOR_RENDER in several places.
 2014-03-10 16:42:42 +08:00
Chia-I Wu
76713ed5d6 ilo: remove intel_bo_get_size() 
Commit bfa8d21759 uses it to work around a
hardware limitation.  But there are other ways to do it without the need for
intel_bo_get_size().
 2014-03-10 16:42:42 +08:00
Chia-I Wu
e7307fe708 ilo: pipe_texture::usage is not a bitfield 
It happens to work because PIPE_USAGE_STAGING is 0x100.
 2014-02-22 22:45:12 +08:00
Chia-I Wu
f8d19a58dc ilo: set ILO_TEXTURE_CPU_WRITE for imported textures 
Assume the bo has been written by another process, which will trigger a HiZ
resolve.
 2014-02-22 22:45:12 +08:00
Chia-I Wu
7fdab3b201 ilo: disable HiZ for misaligned levels 
We need to disable HiZ for non-8x4 aligned levels, except for level 0, layer
0.  For the very first layer we can adjust Width and Height fields of
3DSTATE_DEPTH_BUFFER to make it aligned.

Specifically, add ILO_TEXTURE_HIZ and set the flag only for properly aligned
levels.  ilo_texture_can_enable_hiz() is updated to check for the flag.

In tex_layout_validate(), align the depth bo to 8x4 so that we can adjust
Width/Height of 3DSTATE_DEPTH_BUFFER without introducing out-of-bound access.

Finally in rectlist blitter, add the ability to adjust 3DSTATE_DEPTH_BUFFER.
 2014-01-14 15:43:20 +08:00
Chia-I Wu
1427c3f79f ilo: decide on hiz first in texture allocation 
Add tex_layout_init_hiz() before tex_layout_init_format() to decide whether
HiZ should be enabled.

On GEN6, because of layer offsetting, HiZ is enabled only when the texture is
non-mipmapped and non-array.  PIPE_USAGE_STAGING is also taken as a hint to
disable HiZ.
 2014-01-14 15:43:20 +08:00
Chia-I Wu
c6605c51de ilo: use HALIGN_4 on GEN7 for depth buffers 
The comment was no longer true since 6642381e75.
 2014-01-14 15:42:53 +08:00
Chia-I Wu
e90e3e39c2 ilo: OOM for HiZ is fatal on GEN6 
On GEN6, HiZ and Separate Stencil Buffer must be enabled at the same time.
 2014-01-14 15:19:41 +08:00
Chia-I Wu
5b1c516080 ilo: fix a HiZ bo leakage 
Dereference the HiZ bo when the texture is destroyed.
 2014-01-14 15:19:41 +08:00
Chia-I Wu
76edf44f9e ilo: enable HiZ 
The support is still early.  Fast depth buffer clear is not enabled yet.

HiZ can be forced off with ILO_DEBUG=nohiz.
 2014-01-08 18:11:36 +08:00
Chia-I Wu
846f70a6ef ilo: rename and add an accessor for texture slices 
Rename ilo_texture::slice_offsets to ilo_texture::slices and add an accessor,
ilo_texture_get_slice().
 2014-01-08 18:11:35 +08:00
Chia-I Wu
546416d495 ilo: add support for HiZ allocation 
Add tex_create_hiz() to create HiZ bo.  It is not really called yet.
 2014-01-08 18:11:35 +08:00
Chia-I Wu
e372819589 ilo: refactor separate stencil allocation 
Move separate stencil allocation code to tex_create_separate_stencil to keep
tex_create sane.
 2014-01-08 18:11:35 +08:00
Axel Davy
e8f9195e5f gallium, intel: Implements new __DRI_IMAGE_USE_LINEAR and PIPE_BIND_LINEAR flags to enforce no tiling. 
Signed-off-by: Axel Davy <axel.davy@ens.fr>
 2013-09-06 15:02:34 -07:00
Chia-I Wu
045bf0db52 ilo: honor surface padding requirements 
The PRM specifies several padding requirements that we failed to honor.
 2013-07-10 12:40:22 +08:00
Chia-I Wu
39226705b7 ilo: update winsys interface 
The motivation is to kill tiling and pitch in struct intel_bo.  That requires
us to make tiling and pitch not queryable, and be passed around as function
parameters.
 2013-06-12 17:46:52 +08:00
Chia-I Wu
cdfb2163c4 ilo: get rid of function tables in winsys 
We are moving toward making struct intel_bo alias drm_intel_bo.  As a first
step, we cannot have function tables.
 2013-06-12 17:46:52 +08:00
Chia-I Wu
3f79188854 ilo: remove unnecessary tex_set_bo/buf_set_bo 
Merge the bodies to tex_create_bo/buf_create_bo respectively.
 2013-06-12 17:46:52 +08:00
Chia-I Wu
6b894e6900 ilo: add support for stencil resources on GEN7+ 
For allocations, we need to support stencil-only and separate stencil
resources.  For mapping, we need to support software tiling and
packing/unpacking for separate stencil resources.
 2013-05-16 18:20:17 +08:00
Chia-I Wu
ca349e0217 ilo: simplify ilo_texture_get_slice_offset() 
Always return a tile-aligned offset.  Also fix for W tiling.
 2013-05-15 15:08:54 +08:00
Chia-I Wu
176ad54c04 ilo: rework ilo_texture 
Use ilo_buffer for buffer resources and ilo_texture for texture resources.  A
major cleanup is necessitated by the separation.
 2013-05-14 16:07:22 +08:00
Chia-I Wu
768296dd05 ilo: rename ilo_resource to ilo_texture 
In preparation for the introduction of ilo_buffer.
 2013-05-14 16:01:25 +08:00
Chia-I Wu
528ac68f7a ilo: move transfer-related functions to a new file 
Resource mapping is distinct from resource allocation, and is going to get
more and more complex.  Move the related functions to a new file to make the
separation clear.
 2013-05-14 16:01:20 +08:00
Vinson Lee
5471e3949c ilo: Initialize read_back in transfer_map_sys. 
Fixes "Uninitialized scalar variable" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
 2013-05-10 15:29:40 +08:00
Chia-I Wu
a8e4614071 ilo: add support for PIPE_FORMAT_ETC1_RGB8 
It is decompressed to and stored as PIPE_FORMAT_R8G8B8X8_UNORM on-the-fly.
 2013-05-09 16:05:48 +08:00
Chia-I Wu
183ea823fd ilo: support mapping with a staging system buffer 
It can be used for unpacking compressed texture on-the-fly or to support
explicit transfer flushing.
 2013-05-09 16:05:47 +08:00
Chia-I Wu
baa44db065 ilo: allow for different mapping methods 
We want to or need to use a different mapping method when when the resource is
busy, the bo format differs from the requested format, and etc.
 2013-05-09 16:05:47 +08:00
Chia-I Wu
7cca1aac9d ilo: allow bo format to differ from that requested 
For separate stencil buffer or formats not supported natively, the real format
of the bo may differ from that requested.
 2013-05-09 16:05:47 +08:00
Chia-I Wu
dd62e7bc02 ilo: fix tiling/size for special-purpose resources 
We do not allocate such resources yet though.
 2013-05-01 12:00:32 +08:00
Chia-I Wu
7726e9500c ilo: use UMS layout for render targets 
As we do not advertise MSAA support, this change should not make any
difference yet.
 2013-05-01 11:56:43 +08:00
Chia-I Wu
334abed828 ilo: support and prefer compact array spacing 
There is no reason to waste the memory when the HW can support compact array
spacing (ARYSPC_LOD0).
 2013-05-01 11:31:15 +08:00
Chia-I Wu
bb1f635dcc ilo: add ilo_dev_info shared by the screen and contexts 
The struct is used to describe the device information, such as PCI ID, GEN,
GT, and etc.
 2013-05-01 11:20:41 +08:00
Chia-I Wu
d3602dfac6 ilo: add GEN6 GPE 
GEN6 GPE (Graphics Processing Engine) is a low-level interface to emit 3D
commands and states.
 2013-04-26 16:16:43 +08:00
Chia-I Wu
8f949bc1da ilo: hook up pipe context transfer functions 2013-04-26 16:16:42 +08:00
Chia-I Wu
3a4a570c34 ilo: hook up pipe screen resource functions 2013-04-26 16:16:42 +08:00
Chia-I Wu
63b5720105 ilo: new pipe driver for Intel GEN6+ 
This commit adds some boilerplate code.  The header files found under include/
are copied from i965.
 2013-04-26 16:16:41 +08:00