Commit graph

164303 commits

Author SHA1 Message Date
Vignesh Raman
81a28fb3e2 Do explicit cast to suppress clang warnings
Do explicit cast to suppress the below clang warnings,
../src/mesa/main/get.c:86:31: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
   return ( ((F) * 65536.0f > INT_MAX) ? INT_MAX :

../src/mesa/main/texparam.c:967:27: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
                ((param > INT_MAX) ? INT_MAX : (GLint) (param + 0.5)) :

../src/mesa/main/texparam.c:2609:65: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
         *params = LCLAMPF(obj->Sampler.Attrib.MinLod, INT_MIN, INT_MAX);

../src/mesa/main/texparam.c:2624:65: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
         *params = LCLAMPF(obj->Sampler.Attrib.MaxLod, INT_MIN, INT_MAX);

../src/mesa/main/texparam.c:2648:72: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
         *params = LCLAMPF(obj->Sampler.Attrib.MaxAnisotropy, INT_MIN, INT_MAX);

../src/mesa/main/texparam.c:2693:66: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
         *params = LCLAMPF(obj->Sampler.Attrib.LodBias, INT_MIN, INT_MAX);

../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:731:43: error: implicit conversion from 'unsigned int' to 'float' changes value from 4294967295 to 4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
         OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));

../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:732:43: error: implicit conversion from 'unsigned int' to 'float' changes value from 4294967295 to 4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
         OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));

../src/nouveau/codegen/nv50_ir_peephole.cpp:1647:30: error: implicit conversion from 'unsigned int' to 'float' changes value from 4294967295 to 4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
      CASE(TYPE_U32, u32, 0, UINT32_MAX, 0, INT32_MAX, 0, UINT32_MAX);

../src/nouveau/codegen/nv50_ir_peephole.cpp:1648:38: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
      CASE(TYPE_S32, s32, INT32_MIN, INT32_MAX, INT32_MIN, INT32_MAX, 0, INT32_MAX);

../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:400:51: error: implicit conversion from 'unsigned long long' to 'double' changes value from 18446744073709551615 to 18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
         loads[chan] = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits));

../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:408:43: error: implicit conversion from 'unsigned long long' to 'double' changes value from 18446744073709551615 to 18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
         tmp = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits - 1));

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24362>
2023-09-06 12:38:09 +00:00
Vlad Schiller
3a949de28c pvr: Remove PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC flag
There has been a recent change to the new powervr KMD to always zero buffer
objects at allocation time to avoid information leaks. This change was made to
address upstream feedback [1]. The result is that the
PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC no longer makes a difference when using this
KMD.

As the powervr KMD is the one we actually care about, it makes sense to mirror
this change when using the downstream pvrsrvkm KMD in order to avoid differences
in behaviour between the two KMDs. As this makes the
PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC flag entirely redundant, remove it.

[1] https://lists.freedesktop.org/archives/dri-devel/2023-August/418042.html

Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24930>
2023-09-06 12:19:46 +00:00
Rohan Garg
a57faf5037 iris: migrate preemption streamwout wa to WA infra
Fixes: db6c374 ('iris: disable preemption for 3DPRIMITIVE during streamout')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25080>
2023-09-06 11:51:21 +00:00
Samuel Pitoiset
ed48d1cb53 zink/ci: merge piglit testing with deqp-runner for RADV
This avoids using an extra script to run GLCTS+piglit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25062>
2023-09-06 09:31:00 +00:00
Samuel Pitoiset
b2ce36b40b zink/ci: merge GLCTS testing with GLESx for RADV
Both testsuites used to be executed separately because of spurious
failures/hangs but they seem fixed now.

GLCTS+GLES might be faster to run now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25062>
2023-09-06 09:31:00 +00:00
Samuel Pitoiset
17cd153dd0 radv: add support for DGC with SQTT
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>
2023-09-06 07:52:50 +00:00
Samuel Pitoiset
63e0fcfb13 radv: avoid emitting SQTT markers for DGC calls
This confuses RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>
2023-09-06 07:52:50 +00:00
Jordan Justen
8c8fca53fd intel/genxml: Fix comparing xml when node counts differ
This fix is more relevant to MR !20593. Normally when sorting the
number of nodes will be equivalent today, so this bug will not be
encountered. But in !20593, we can shrink (--import) or grow the
number of elements (--flatten) when the genxml_import.py tool is used.

Fixes: e60a0b1616 ("intel/genxml: Move sorting & writing into GenXml class")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24902>
2023-09-06 07:18:47 +00:00
Jordan Justen
d8038c8d09 intel/genxml: Ignore tail leading/trailing whitespace in node_validator()
When importing or flattening genxml with the genxml_import.py script
in MR !20593, it can lead to the tail portion of xml items differing
in whitespace.

If we strip the trailing and leading whitespace from the tail string,
and the strings are equivalent, then we can consider the xml items to
be equivalent.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24903>
2023-09-06 06:51:48 +00:00
Jordan Justen
5d37359f32 intel/dev/xe: Move placeholder subslice info into XEHP_FEATURES
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24418>
2023-09-05 23:02:42 -07:00
Chris Spencer
9123505dde radv/video: use correct enum value for max level IDC
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>
2023-09-06 05:10:33 +00:00
Chris Spencer
c29e3d5205 anv/video: use correct enum value for max level IDC
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>
2023-09-06 05:10:33 +00:00
Marek Olšák
3040aa2e26 ac/llvm: don't convert undef to 0 because nir_opt_undef does it now
TOTALS FROM AFFECTED SHADERS (29663/58918)
  Code Size: 39163724 -> 37842360 (-3.37 %) bytes
  Max Waves: 394813 -> 396334 (0.39 %)
  Outputs: 84616 -> 84616 (0.00 %)
  Patch Outputs: 0 -> 0 (0.00 %)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
2023-09-06 03:24:16 +00:00
Marek Olšák
497c40be19 nir: remove nir_op_unpack_64 handling from nir_opt_undef
It's no longer needed because undef is replaced with 0 in this case.

It also has a bug that it doesn't freeze the undef value if undef has
multiple uses.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
2023-09-06 03:24:16 +00:00
Marek Olšák
861d274453 nir: replace undef only used by ALU opcodes with 0 or NaN
If undef is consumed by an FP opcode, replace it with NaN to eliminate
that opcode, else replace it with 0, but there are exceptions, such as
when undef is used by stores or phis, it's not touched.

This also contains workarounds for viewperf shaders.

radeonsi:
TOTALS FROM AFFECTED SHADERS (1987/58918)
  Code Size: 5158692 -> 5143796 (-0.29 %) bytes
  Max Waves: 22456 -> 22513 (0.25 %)
  Outputs: 3726 -> 3726 (0.00 %)
  Patch Outputs: 0 -> 0 (0.00 %)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
2023-09-06 03:24:16 +00:00
Jordan Justen
2b128c570b intel/clflush: Add support for clflushopt instruction
Rework:
 * Split clflushopt into a separate file as recommended by Ken.
   If we enable -mclflush on all driver source compilation, then
   gcc may insert uses of it on processors that don't support it.
 * Add uintptr_t casting to cpu_caps->cacheline usage

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
2023-09-06 01:39:53 +00:00
Jordan Justen
6f30c980dd util/u_cpu_detect: Detect clflushopt support
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
2023-09-06 01:39:53 +00:00
Jordan Justen
159c797362 util/u_cpu_detect: Drop unused has_tsc
This will allow us to add has_clflushopt without spilling into an new
unsigned.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
2023-09-06 01:39:53 +00:00
Jordan Justen
e111d3241a anvil,hasvk: Use intel_flush_range_no_fence to flush command buffers
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
2023-09-06 01:39:53 +00:00
Jordan Justen
9f20be64e6 intel/common: Add intel_flush_range_no_fence
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
2023-09-06 01:39:53 +00:00
Jordan Justen
486e7bdbd8 anvil,hasvk: Replace intel_clflush_range with intel_flush_range
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
2023-09-06 01:39:53 +00:00
Jordan Justen
543a707b7b intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
2023-09-06 01:39:53 +00:00
Jordan Justen
735026e811 anvil,hasvk: Rename need_clflush to need_flush
$ git grep -l need_clflush | xargs sed -i 's/need_clflush/need_flush/g'

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
2023-09-06 01:39:53 +00:00
Karol Herbst
785d96b040 rusticl/mesa: create contexts with PIPE_CONTEXT_NO_LOD_BIAS
It's not a thing in OpenCL

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25067>
2023-09-06 01:23:34 +00:00
Sil Vilerino
8d79376957 d3d12: Video Decode - Remove unnecessary copy for texture array case
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25069>
2023-09-06 01:05:36 +00:00
antonino
1456cb9c0b drirc: enable vk_wsi_force_swapchain_to_current_extent for "Serious Sam Fusion"
This game handles swapchain size incorrecly and can crash because of
it.

Enable this driconf as a workaround.

Fixes: 6139493ae3 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
2023-09-06 00:10:41 +00:00
antonino
142e317024 drirc: enable vk_wsi_force_swapchain_to_current_extent for "The Talos Principle"
This game handles swapchain size incorrecly and can crash because of
it.

Enable this driconf as a workaround.

Fixes: 6139493ae3 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
2023-09-06 00:10:41 +00:00
antonino
aa657247ce vulkan/wsi: add vk_wsi_force_swapchain_to_current_extent driconf
Add a driconf to force the swapchain size to match
`VkSurfaceCapabilities2KHR::currentExtent` as a workaround for
misbehaved games

Fixes: 6139493ae3 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
2023-09-06 00:10:41 +00:00
Dave Airlie
d45f598ece llvmpipe: move to nir lowering for fquantize2f16
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24988>
2023-09-05 23:33:20 +00:00
Tapani Pälli
b6bd7107e6 driconf: use lower_depth_range_rate for The Spirit and The Mouse
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9738
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25029>
2023-09-05 22:40:36 +00:00
David Rosca
ad6557b101 frontends/va: Support chroma sample location in postproc
Rename vlVaSetCscMatrix to vlVaSetProcParameters because it now does
more than just setting csc matrix.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
2023-09-05 21:31:43 +00:00
David Rosca
a50a46acf5 gallium/auxiliary/vl: Support chroma sample location in compute shaders
Used only in YUV to RGB video_buffer shader for now.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
2023-09-05 21:31:43 +00:00
David Rosca
a6a43963ed gallium/auxiliary/vl: Clamp coordinates in compute shaders
Video textures include padding, so this is needed to avoid sampling
outside of src rect due to scaling or additional offset.
Fixes wrong colors on right/bottom edge.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
2023-09-05 21:31:43 +00:00
David Rosca
a90b9f1d1e gallium/auxiliary/vl: Map range when updating constants
Use WRITE | DISCARD_RANGE to avoid having to read back the csc matrix
and luma min/max values.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
2023-09-05 21:31:43 +00:00
David Rosca
7c8e1596d6 gallium/auxiliary: Fix util_compute_blit half texel offset with scaling
Video textures include padding, so make sure to not sample outside
src rect. Also remove the parameter and always use the offset.

When not scaling, this fixes blurry output.
When scaling, this fixes incorrect color at right/bottom edge.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
2023-09-05 21:31:43 +00:00
Mike Blumenkrantz
959801d9d9 zink: polaris ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25056>
2023-09-05 19:43:46 +00:00
Alyssa Rosenzweig
07cb81f0fc asahi: Skip LOD bias lowering for GLES
This reduces silliness in Dolphin ubershaders by eliminating the double
lowering. It also makes the GLES shader assembly nicer to read.

Dolphin ubershader performance at 4K on MMG improved by about 0.5%. Not massive,
but definitely noticeable and reduces the delta to macOS.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:35 +00:00
Alyssa Rosenzweig
2adb0f31fc gallium,mesa/st: Add PIPE_CONTEXT_NO_LOD_BIAS flag
While desktop GL supports sampler LOD bias, GLES does not. To support the GL use
case, all Gallium drivers are expected to handle sampler LOD bias. However, this
may require shader code to implement (lowering tex to txb, txl to fadd+txl) and
cost resources to push the LOD bias constants into the shader. The issue is
compounded with something like Dolphin's GLES renderer, which does this LOD bias
emulation itself -- meaning that LOD bias is lowered twice when using Dolphin
with GLES! As such, this commit adds a context flag for frontends to communicate
that they will never use sampler LOD bias, allowing the driver to omit the
lowering as a GLES fast path (or, for Dolphin, for performance parity between
GLES and GL).

This will be used on Asahi. It could also be used to optimize a path on
Mali-T720 supported in Panfrost, though I don't intend to write that patch.

Originally https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25034

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
6269b60a1c asahi: Conditionally expose cube arrays
With =deqp. I don't want this exposed before geometry shaders since we run dEQP
(GLES) far more than Piglit (GL), and we need geometry shaders to get adequate
regression testing via dEQP-GLES.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
dd3dd6e127 asahi: Handle linear 1D Arrays
Lowered to linear 2D Arrays, handle them like that. Fixes 1D Array case of
arb_shader_image_size-builtin.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
56267ec14d asahi: Forbid linear 1D Array images
Porbably a theoretical case, but these fall down the 2D path so better not allow
it at any rate.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
fb60626260 agx: Run opt_idiv_const after lowering texture
Shaves 10 instructions off the cube map array lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
49951ef3cc agx: Lower coordinates for cube map array images
Annoyingly different from texture coordinates.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
fb76f6cc6e agx: Handle cube arrays when clamping arrays
Need to adjust the component.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
54ebddaa0f ail: Force page-alignment for layered attachments
When rendering to a layered depth/stencil attachment, we specify the layer
stride in pages. That means that depth/stencil targets must be page-aligned to
be rendered to correctly.

If we're merely sampling, not rendering, we do not need the extra alignment. So
we add a flag to handle this case so we keep passing the generated ail tests.

Fixes KHR-GLES31.core.texture_cube_map_array.color_depth_attachments

Similarly, we page-align colour attachments. I don't have a good theoretical
justification for this part, but it seems to be necessary and layered rendering
fails otherwise. Possibly the PBE requires page-aligned layers unconditionally?

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
f9b08cf3a6 asahi: Translate cube array dimension
Yet another enum.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
7895d5b79c agx: Add unit test for cmp+sel fusing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
bdad7992bc agx: Add unit test for if_cmp fusing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
08e0c5a9cf agx: Fuse compares into selects
This lets us save a LOT of instructions at the cost of increased register
pressure. However, on my shader-db, this is still coming out ahead since no
shaders are hurt for thread count/spills, and only 1/10 of the shaders helped
for instruction count are hurt for register pressure. The shaders most hurt
for pressure have very low pressure (7 -> 15 is the worst case) and you need a
certain number of registers to use a 4 source instruction at all. Analyzing the
hurt shaders, nothing concerns me too much ... this isn't as bad as I feared.

So I think at this point it's worth ripping off the bandage, given the massive
potential for instruction count win. This is a big improvement for some of the
shaders I'm working on for my $SECRET_PROJECT.

   total instructions in shared programs: 1784943 -> 1775169 (-0.55%)
   instructions in affected programs: 644211 -> 634437 (-1.52%)
   helped: 3498
   HURT: 38
   Instructions are helped.

   total bytes in shared programs: 11720734 -> 11643224 (-0.66%)
   bytes in affected programs: 4370986 -> 4293476 (-1.77%)
   helped: 3572
   HURT: 36
   Bytes are helped.

   total halfregs in shared programs: 474094 -> 475165 (0.23%)
   halfregs in affected programs: 12821 -> 13892 (8.35%)
   helped: 65
   HURT: 247
   Halfregs are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
e7ffc799d1 agx: Fuse conditions into if's
Simple greedy thing that has the potential to inflate register pressure but
reduces instructions. Thanks to the recent loop work that turns if { break }
into while_icmp, this also implicitly handles fusing conditions into loops,
which is what actually prompted this.

Surprisingly, this helps register pressure on my shader-db (no change to thread
count), I guess by eliminating the boolean temps in case where the sources are
used multiple times.

   total instructions in shared programs: 1786561 -> 1784943 (-0.09%)
   instructions in affected programs: 128557 -> 126939 (-1.26%)
   helped: 474
   HURT: 13
   Instructions are helped.

   total bytes in shared programs: 11733236 -> 11720734 (-0.11%)
   bytes in affected programs: 976034 -> 963532 (-1.28%)
   helped: 521
   HURT: 13
   Bytes are helped.

   total halfregs in shared programs: 474245 -> 474094 (-0.03%)
   halfregs in affected programs: 1869 -> 1718 (-8.08%)
   helped: 28
   HURT: 7
   Halfregs are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00