I somehow thought this list was sorted roughly alphabetical, but it's
actually sorted by the extension number. Whoops, let's fix that.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27452>
It's pointless to increase the refcount of the backing BO and then decrease
it in the same function when we already reference the slab entry BO that
holds the reference of the backing BO.
amdgpu_do_add_buffer is inlined in amdgpu_cs_submit_ib, so the new parameter
doesn't cost anything.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
We unset RADEON_USAGE_SYNCHRONIZED, but we still checked it.
Iterate over such buffers separately without checking
RADEON_USAGE_SYNCHRONIZED.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
The first loop updates sequence numbers. The second loop creates the BO list.
Do both in the same loop.
Each loop has to reload the whole BO list from the L2 cache or higher, so we
do it twice. By merging the loops, we only load the BO list from the L2
cache once.
The final result is actually 2 loops, but they iterate over different ranges
of the BO list, so each element is read only once.
If global_bo_list is enabled, it overwrites the BO list after all is done.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
The first loop is inside amdgpu_add_sparse_backing_buffers. The second loop
iterates over sparse BOs to update sequence numbers.
Each loop has to reload the whole BO list from the L2 cache or higher, so we
do it twice. By merging the loops, we only load the BO list from the L2
cache once.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
The first loop is inside amdgpu_add_slab_backing_buffers. The second loop
iterates over BOs to update sequence numbers.
Each loop has to reload the whole BO list from the L2 cache or higher, so we
do it twice. By merging the loops, we only load the BO list from the L2
cache once.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
Ref: 0a52002a1c ("anv: disable reset query pools using blorp opt on MTL")
Ref: b3b12c2c27 ("anv: enable CmdCopyQueryPoolResults to use shader for copies")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
Ref: bspec 55414
Ref: 951e08fc18 ("intel/compiler: Disable DPAS instructions on MTL")
Suggested-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
MTL and ARL share many code paths, and this macro will make it easier
to check for either of them.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352>
When GS will be compiled separately, we will have to always declare
both VS and TES user SGPRs because we can't know the previous stage,
and the shader input arguments must match and mustn't overlap.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27431>
This will help implementing VS+GS and TES+GS compiled separately on
GFX9+ because the shader config will need to be combined.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27431>
