Commit graph

31576 commits

Author SHA1 Message Date
Eric Anholt
7f80a9ff13 vc4: Introduce XML-based packet header generation like Intel's.
I really liked this idea, as it should help with management of packet
parsing tools like the CL dump.  The python script is forked off of theirs
because our packets are byte-based instead of dwords, and the changes to
do so while avoiding performance regressions due to unaligned accesses
were quite invasive.

v2: Fix Android.mk paths, drop shebang for python script, fix overlap
    detection.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Rob Herring <robh@kernel.org>
2017-06-30 12:25:45 -07:00
Bruce Cherniak
6646f6ba0d swr: Minor cleanup of variable usage, no functional change.
In swr_update_derived, for consistency, index buffer validation should
be using the p_draw_info copy "info" rather than referencing
p_draw_info.

No functional change.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
b9b53e2695 swr: use swr_query_result type instead of void
Tag pStat field in swr_draw_context structure so gen_llvm_types.py
can deal with the actual structure type instead of using void.

Code cleanup, no functional change.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
80bd5cd9d0 swr/rast: increase number of possible draws in flight
Increases performance of some large workloads on KNL by ~30%.

Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
ab564c7ab4 swr/rast: move default split size from driver to rasterizer
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
64af92c977 swr/rast: Fix missing setup of psContext.pColorBuffer
Fixes render target read access from pixel shaders.

Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
fc4f6c44c4 swr/rast: Switch intrinsic usage to SIMDLib
Switch from a macro-based simd intrinsics layer to a more C++
implementation, which also adds AVX512 optimizations to 128-bit
and 256-bit SIMD.

Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
614de92f10 swr/rast: Fix unused variable warnings
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
0cc7c46cf4 swr/rast: Split rasterizer.cpp to improve compile time
Hardcode split to four files currently.  Decreases swr build
time on KNL by over 50%.

Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
5eecaca911 swr/rast: gen_backends.py remove extraneous semicolon
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
f87ff64850 swr/rast: Support dynamically sized vertex layout
Each shader stage state (VS, TS, GS, SO, BE/CLIP) now has a
vertexAttribOffset to specify the offset to the start of the
general attribute section of the incoming verts for that stage.
It is up to the driver to set this up correctly based on the
active stages. All the shader stages use this value instead of
VERTEX_ATTRIB_START_SLOT to offset to the incoming attributes.

Only the vertex shader stage supports dynamic layout output
currently. The other stages continue to expect the output to be
the fixed layout slots as before. Will be enabling GS next.

Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
cae53b24d7 swr/rast: Split backend.cpp to improve compile time
Hardcode split to four files currently.  Decreases swr build
time on a quad-core by ~10%.

Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
b89bd3694c swr/rast: gen_backends.py removal of commented debug prints
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
248663f91d swr/rast: gen_backends.py quote cleanup
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Tim Rowley
ba64ddedc2 swr/rast: generators will create target directories
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-30 13:26:19 -05:00
Mauro Rossi
84690d06c1 Android: fix typo in symlink for driver loading and 32 bit builds
There is typo in the mkdir command path,
the correct one is $(TARGET_OUT)/$(l)/$(MESA_DRI_MODULE_REL_PATH)

The other issue is in 32bit builds, because lib64 does not exist there,
we can use TARGET_IS_64_BIT to refine the post install command.

Fixes: a3d98ca62f ("Android: use symlinks for driver loading")

Signed-off-by: Rob Herring <robh@kernel.org>
2017-06-30 11:23:51 -05:00
Brian Paul
0782350b80 svga: update a few surface format names
To sync with in-house changes.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-06-30 08:24:27 -06:00
Brian Paul
d3cbe8c5f3 svga: whitespace fixes in svga_resource_buffer_upload.c
Trivial.
2017-06-30 08:24:27 -06:00
Charmaine Lee
5e5d5f1a2e svga: add mksstats for surface view emulation
Add mksstats for surface view emulation and also tighten the stat
CreateBackedView for the actual creation of backed view.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-06-30 08:24:27 -06:00
Brian Paul
4f3974d758 svga: change error handling convention for svga_set_stream_output()
In general, the functions which emit commands to the command buffer check
for failure and return a PIPE_ERROR_x code.  It's up to the caller to
flush the buffer and retry the command.

But svga_set_stream_output() did its own flushing and the callers never
checked the return value (though, it would always be PIPE_OK) in practice.

This patch changes svga_set_stream_output() so that it does not call
svga_context_flush() when the buffer is full.  And we update the callers
to check the return value as we do for other functions, like
svga_set_shader().

No Piglit regressions.  Also tested w/ Nature demo.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-06-30 08:24:27 -06:00
Charmaine Lee
adead35320 svga: fixed surface size to include array size
This patch fixes the total surface size in surface cache
to include array size as well.

Tested with MTT glretrace.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-06-30 08:24:27 -06:00
Neha Bhende
31fe1d10b2 svga: loop over box.depth for ReadBack_image on each slice
piglit test ext_texture_array-gen-mipmap is fixed with this patch.

Tested with mtt piglit, glretrace, viewperf and conform. No regression.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-06-30 08:24:27 -06:00
Charmaine Lee
203d88460c svga: add mksstats for context creation
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-06-30 08:24:27 -06:00
Charmaine Lee
dbb5d2a790 svga: re-validate sampler view at draw time if needed
This patch validates those sampler views with backing copy
of texture whose original copy has been updated since the
view is last validated.
This is done here at draw time because the texture binding might not
have modified, hence validation is not triggered at state update time,
and yet the texture might have been updated in another context, so
we need to re-validate the sampler view in order to update the backing
copy of the updated texture.

This fixes a rendering flickering issue with Photoshop running in
Linux VM with HWversion 11. The problem is Photoshop renders to texture A
in context X, and then bind texture A to context Y. The first time
when texture A is bound to context Y, cso calls pipe->set_sampler_views().
Validation of sampler views is done, rendering is fine.
But when texture A is rendered to again in context X, and rebound in
context Y, cso skips pipe->set_sampler_views() because texture A is already
bound in context Y. SVGA driver is not given a chance to re-validate
the texture binding, the backing copy of the texture is not updated,
and hence causes black image.

Tested with Photoshop, MTT glretrace, piglit.
Fixes VMware bug 1769103.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-06-30 08:24:27 -06:00
Rob Herring
cceb2d5c41 gallium: os_process fixes for Android
The function getprogname() is available on Android, since it reuses
various BSD solutions C runtime.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-30 08:44:19 +01:00
Tomeu Vizoso
2ecdedb8d4 etnaviv: Add unreachable statement to etna_amode to fix compilation warnings
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-30 08:44:16 +01:00
Bruce Cherniak
277621bbb7 swr: Remove need to allocate vertex buffer scratch space all in one go
Deferred deletion (via "fence_work") has obsoleted the need to allocate
all client vertex buffer scratch space in a single chunk.  Scratch
allocations are now valid until the referenced fence is complete.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-06-29 13:23:33 -05:00
Bruce Cherniak
2b27dcd075 swr: conditionally validate vertex buffer state
Vertex buffer state doesn't need to be validated on every call,
only on dirty _NEW_VERTEX or indexed draws.

Unconditional validation was introduced as part of patch 330d0607ed,
"remove pipe_index_buffer and set_index_buffer", with the expectation
we'd optimize later.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-06-29 13:23:33 -05:00
Tim Rowley
867e111769 swr: set dynamic vertex size
Reduces the memory footprint of the frontend processing by packing
vertices.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-29 13:23:33 -05:00
Marek Olšák
ccfac28835 radeonsi: set COMPUTE_DISPATCH_INITIATOR.ORDER_MODE = 1
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-29 16:19:35 +02:00
Marek Olšák
af52e61935 radeonsi: use the DISPATCH packets to force COMPUTE_START_X/Y/Z = 0
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-29 16:19:35 +02:00
Rob Herring
a3d98ca62f Android: use symlinks for driver loading
Instead of having special driver loading logic for Android, create
symlinks to gallium_dri.so so we can use the standard loading logic.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-06-29 09:09:49 -05:00
Lucas Stach
4fb9f97047 etnaviv: fix memory leak when BO allocation fails
The resource struct is already allocated at this point and should be
freed properly.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-06-29 11:34:50 +02:00
Lucas Stach
b2a87ce34f etnaviv: fill in layer_stride for imported resources
The layer stride information is used in various parts of the driver,
so it needs to be present regardless if the driver allocated the
buffer itself or merely imported it from an external source.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-06-29 11:34:24 +02:00
Lucas Stach
ec43605189 etnaviv: fix shader miscompilation with more than 16 labels
The labels array may change its virtual address on a reallocation, so
it is invalid to cache pointers into the array. Rather than using the
pointer directly, remember the array index.

Fixes miscompilation of shaders in glmark2 ideas, leading to GPU hangs.

Fixes: c9e8b49b (etnaviv: gallium driver for Vivante GPUs)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-06-28 22:04:30 +02:00
Marek Olšák
4a10d6154e radeonsi: move instance divisors into a constant buffer
Shader key size: 107 -> 47

Divisors of 0 and 1 are encoded in the shader key. Greater instance divisors
are loaded from a constant buffer.

The shader code doing the division is huge. Is it something we need to
worry about? Does any app use instance divisors >= 2?

VS prolog disassembly:
    s_load_dwordx4 s[12:15], s[0:1], 0x80  ; C00A0300 00000080
    s_nop 0                                ; BF800000
    s_waitcnt lgkmcnt(0)                   ; BF8C007F
    s_buffer_load_dword s14, s[12:15], 0x4 ; C0220386 00000004
    s_waitcnt lgkmcnt(0)                   ; BF8C007F
    v_cvt_f32_u32_e32 v4, s14              ; 7E080C0E
    v_rcp_iflag_f32_e32 v4, v4             ; 7E084704
    v_mul_f32_e32 v4, 0x4f800000, v4       ; 0A0808FF 4F800000
    v_cvt_u32_f32_e32 v4, v4               ; 7E080F04
    v_mul_hi_u32 v5, v4, s14               ; D2860005 00001D04
    v_mul_lo_i32 v6, v4, s14               ; D2850006 00001D04
    v_cmp_eq_u32_e64 s[12:13], 0, v5       ; D0CA000C 00020A80
    v_sub_i32_e32 v5, vcc, 0, v6           ; 340A0C80
    v_cndmask_b32_e64 v5, v6, v5, s[12:13] ; D1000005 00320B06
    v_mul_hi_u32 v5, v5, v4                ; D2860005 00020905
    v_add_i32_e32 v6, vcc, v5, v4          ; 320C0905
    v_subrev_i32_e32 v4, vcc, v5, v4       ; 36080905
    v_cndmask_b32_e64 v4, v4, v6, s[12:13] ; D1000004 00320D04
    v_mul_hi_u32 v5, v4, v1                ; D2860005 00020304
    v_add_i32_e32 v4, vcc, s8, v0          ; 32080008
    v_mul_lo_i32 v6, v5, s14               ; D2850006 00001D05
    v_add_i32_e32 v7, vcc, 1, v5           ; 320E0A81
    v_cmp_ge_u32_e64 s[12:13], v1, v6      ; D0CE000C 00020D01
    v_sub_i32_e32 v6, vcc, v1, v6          ; 340C0D01
    v_cmp_le_u32_e32 vcc, s14, v6          ; 7D960C0E
    v_cndmask_b32_e64 v8, 0, -1, s[12:13]  ; D1000008 00318280
    v_cndmask_b32_e64 v6, 0, -1, vcc       ; D1000006 01A98280
    v_and_b32_e32 v6, v8, v6               ; 260C0D08
    v_cmp_eq_u32_e32 vcc, 0, v6            ; 7D940C80
    v_cndmask_b32_e32 v6, v7, v5, vcc      ; 000C0B07
    v_add_i32_e32 v5, vcc, -1, v5          ; 320A0AC1
    v_cmp_eq_u32_e32 vcc, 0, v8            ; 7D941080
    v_cndmask_b32_e32 v5, v6, v5, vcc      ; 000A0B06
    v_add_i32_e32 v5, vcc, s9, v5          ; 320A0A09

v2: set prefer_mono for fetched instance divisors

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-27 19:55:09 +02:00
Marek Olšák
aef998fe4b radeonsi: check nr_cbufs in other places before flushing CB
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-27 18:46:12 +02:00
Marek Olšák
f9a7e7fe14 radeonsi: use #pragma pack to pack si_shader_key
sizeof(struct si_shader_key):
  Before reverting the 2 commits: 120 bytes
  After reverting the 2 commits: 128 bytes
  With #pragma pack: 107 bytes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-27 18:45:07 +02:00
Marek Olšák
77d2a98353 Revert "radeonsi: use uint32_t to declare si_shader_key.opt.kill_outputs"
This reverts commit 7b2240ac9c.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-27 18:45:07 +02:00
Marek Olšák
dbe45e1180 Revert "radeonsi: remove 8 bytes from si_shader_key with uint32_t ff_tcs_inputs_to_copy"
This reverts commit 6b6fed3a3c.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-27 18:45:07 +02:00
Leo Liu
fad0b47219 radeon/vcn: enable h264 decode entension support
It's enabled through message buffer for UVD

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-06-27 10:59:44 -04:00
Charmaine Lee
b2e78e79d7 svga: clean up format_cap_table
Per Jose's suggestion, this patch cleans up format_cap_table to remove
the unnecessary default cap value for vgpu10 formats since those devcap values
can be retrieved from the device.

Tested with MTT conform, glretrace, piglit in HWv13 and HWv8.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-06-27 07:49:03 -06:00
Charmaine Lee
122ca27a48 svga: fix the default devcap for SVGA3D_Z_D24S8_INT
The default devcap for format SVGA3D_Z_D24S8_INT in HWv8 when its devcap is
not explicitly advertised should be set to zero to match the default value
in the device.

Tested with MTT piglit in HW version 8.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-06-27 07:49:02 -06:00
Charmaine Lee
eea6223184 svga: create buffer surfaces for incompatible bind flags
In cases where certain bind flags cannot be enabled together,
such as CONSTANT_BUFFER cannot be combined with any other flags,
a separate host surface will be created.
For example, if a stream output buffer is reused as a constant buffer,
two host surfaces will be created, one for stream output,
and another one for constant buffer. Data will be copied from the
stream output surface to the constant buffer surface.

Fixes piglit test ext_transform_feedback-immediate-reuse-index-buffer,
                  ext_transform_feedback-immediate-reuse-uniform-buffer

Tested with MTT piglit, MTT glretrace, Nature, NobelClinician Viewer, Tropics.

v2: Fix bind flags compatibility check as suggested by Brian.
v3: Use the list utility to maintain the buffer surface list.
v4: Use the SAFE rev of LIST_FOR_EACH_ENTRY

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-06-27 07:49:02 -06:00
Charmaine Lee
7abfb0b0d5 svga: do not unconditionally enable streamout bind flag
Currently we unconditionally enable streamout bind flag at
buffer resource creation time. This is not necessary if the buffer
is never used as a streamout buffer. With this patch, we enable
streamout bind flag as indicated by the state tracker. If the buffer
is later bound to streamout and does not already has streamout bind
flag enabled, we will recreate the buffer with
the new set of bind flags. Buffer content will be copied
from the old buffer to the new one.

Tested with MTT piglit, Nature, Tropics, Lightsmark.

v2: Fix bind flags check as suggested by Brian.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-06-27 07:49:02 -06:00
Charmaine Lee
b549f5e6b1 svga: pass tobind_flags to svga_buffer_handle
This is to prepare for more bind_flags optimization
in subsequent patches.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-06-27 07:49:02 -06:00
Charmaine Lee
4a79b508a4 svga: pass bind_flags to surface create functions
This is to prepare for other bind_flags optimization
in subsequent patches.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-06-27 07:49:02 -06:00
Brian Paul
ce608784d0 pipe_loader_sw: fix compilation warning
Add the new 'flags' parameter to pipe_loader_sw_create_screen().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-27 07:49:02 -06:00
Lionel Landwerlin
3c50ebce25 i915: use different CFLAGS/LIBS variables than i965/anv
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-27 14:10:29 +03:00
Ilia Mirkin
4a79f2be33 nv50/ir: fix combineLd/St to update existing records as necessary
Previously the logic would decide that the record is kept, which
translates into keep = false in the caller, which meant that these
passes did not run.

While it's right that keep = false which means that a new record does
not need to be added, we do still have to perform the usual list
maintenance. It's easiest to do this pre-merge rather than post.

The lowering that clip/cull distance passes produce triggers this bug in
TCS (since reading outputs is done differently in other stages), but it
should be possible to achieve it with the right sequence of regular
reads/writes.

Fixes: KHR-GL45.cull_distance.functional
Fixes: generated_tests/spec/arb_tessellation_shader/execution/tes-input/tes-input-gl_ClipDistance.shader_test
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2017-06-26 20:24:19 -04:00