Commit graph

6513 commits

Author SHA1 Message Date
Daniel Schürmann
7f40dc9760 aco: simplify multiply-add combining
When both operands of a v_sub (same apply for v_add) are mul and one
already uses clamp/omod, pick the other operand to get a chance to
combine to a MAD.

No fossils-db changes.

Co-authored-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 01134b0bfe)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
12c0bfaaf9 radv: vectorize 16bit instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit fcd2ef23e5)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
6a7552aa10 aco: emit packed 16bit instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 454bbf8f23)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
01a7662154 aco: create helpers to emit vop3p instructions
Also make get_alu_src() capable to return
unswizzled multi-component SGPR sources.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 5ad52ac906)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
65288fe496 aco: change usesModifiers() considering opsel_hi on packed instructions
opsel_hi == 1 means that the high operand selects the
high bits of the input, which is the normal behavior.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 036a369f46)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
0319695645 aco: allow SGPRs on every src position for VOP3P
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 178b33c870)
2021-01-13 11:24:10 -08:00
Daniel Schürmann
126cc30440 aco: allow constants/literals on every src position for VOP3P
and prevent literals on VOP3P pre-GFX10.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 0db4263a3a)
2021-01-13 11:24:10 -08:00
Daniel Schürmann
3714b68ec1 aco/RA: fix subdword operands on VOP3P instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 4a75a28698)
2021-01-13 11:24:10 -08:00
Daniel Schürmann
ac4caa502f aco: fix VOP3P assembly, VN and validation
aco/opcodes: rename v_pk_fma_mix* -> v_fma_mix*
and add modifier capabilities for VOP3P.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 2caba08c1a)
2021-01-13 11:24:10 -08:00
Samuel Pitoiset
3c1275ccae radv: enable DCC for MSAA on GFX10+
It should work fine now.

This gives +1-2% improvements with Control MSAA (2x and 4x)
on Sienna.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8413>
2021-01-13 17:24:31 +00:00
Bas Nieuwenhuizen
4a783a3c78 radv: Use L2 coherency on GFX9+.
Especially on GFX10 we can avoid pretty much all L2 flushes.

However, instead of that we have to do L2_METADATA invalidations. We
do that every time we could possibly be reading new DCC/HTILE info
from the L2 cache in shaders.

Benchmark results, basemark on high preset with a navi10 on profile_standard
(which is slower than a navi10 on default settings, please don't compare
 to random navi10 results you find)

before:
  5932
  5928
  5937

after:
  6011
  6013
  6009

So this looks like a >1% increase.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
0af86341a2 radv: Use L2 for CP DMA on GFX9+.
This enables assuming that the L2 is always up to date for barriers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
8f8d72af55 radv: Use access helpers for flushing with meta operations.
This way we're properly using the vulkan barrier paradigm instead
of adhoc guessing what caches need to be flushed. This is more robust
for cache policy changes as we now don't have to revisit all the meta
operations all the time.

Note that a barrier has both a src and dst part though. So

barrier:
   flush src
   meta op
   flush dst

becomes

barrier:
  flush barrier src
  flush meta op dst
  meta op
  flush meta op src
  flush barrier dst

And there are some places where we've been able to replace a CB flush
with a shader flush because that is what we'd need according to vulkan rules
(and it turns out that in the cases the CB flush mattered the app will set the
bit in one of the relevant flushes or it was needed as a result of an optimization
that we counter-acted in the previous patch.)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
dba0a523a0 radv: Do dst invalidations for write accesses.
For write-after-write hazards.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
9026f10cda radv: Invalidate CB on SHADER_WRITE for meta operations.
To cancel the optimization in radv_dst_access_flush if these helpers
get used by meta operations.

We could also remove that optimization but I think this triggers less
often as all SHADER_WRITE flushes on images not supporting STORAGE should
be meta

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
3d7713b5a2 radv: Remove redundant WB_L2 flush.
INV_L2 already does that.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Samuel Pitoiset
afad13700a radv: disable VK_EXT_sample_locations again on GFX10+
I attempted to enable it for 21.0, only 2x and 4x were supported
but there is new failures if DCC+MSAA is enabled.

Disable it again because DCC is more important than this feature and
no Mesa releases have it on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8472>
2021-01-13 15:04:56 +00:00
Samuel Pitoiset
001c1105f1 radv: enable DCC for mipmaps on GFX10+
Seems to work fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
2021-01-13 13:42:04 +00:00
Samuel Pitoiset
825e2386dc radv: do not enable DCC for 3D images with mipmaps on GFX10+
This is broken for some reasons, and probably rare enough to
care for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
2021-01-13 13:42:04 +00:00
Samuel Pitoiset
755a8313fc radv: add support for fast-clearing DCC levels on GFX10+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
2021-01-13 13:42:04 +00:00
Samuel Pitoiset
5537c9de73 radv: prevent fast-clearing uncompressed DCC levels
When size is 0, this means the level can't be compressed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
2021-01-13 13:42:04 +00:00
Samuel Pitoiset
a4876f055c ac/surface: store DCC mip info into the surface
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
2021-01-13 13:42:04 +00:00
Rhys Perry
8301d483ff aco/tests: don't rely on argument evaluation order
The argument evaluation order is implementation-defined and affects the
order the instructions are inserted.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3938
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7945>
2021-01-13 13:04:26 +00:00
Samuel Pitoiset
fcd5925612 radv: skip fast-clear eliminate for CMASK based on a predicate
If we have CMASK, we can also skip FCE like we do for DCC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8332>
2021-01-13 12:24:32 +01:00
Samuel Pitoiset
697c93abc1 radv: update the FCE predicate for fast clears using CMASK
Fast clearing with CMASK should always be eliminated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8332>
2021-01-13 12:24:30 +01:00
Samuel Pitoiset
051e2bfe80 radv: allocate and initialize the FCE predicate value for CMASK too
In case we don't have DCC, we can still predicate FCE with CMASK.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8332>
2021-01-13 12:24:29 +01:00
Samuel Pitoiset
735b808639 radv: only use predication if the FCE value is allocated
The FCE predicate value is only allocated if DCC is enabled.
We only want to use predication for DCC decompressions and for FCE
but not having FMASK doesn't mean the predicate is allocated.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4075
Fixes: 6e7008e94b ("radv: do not predicate FMASK decompression when DCC+MSAA is used")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8441>
2021-01-13 11:13:47 +00:00
Samuel Pitoiset
dbe845624b radv: fix clearing DCC on GFX9
dcc_slice_size is in DWORD on GFX9... Also, layers aren't supported
because they might be interleaved. Fix this by clearing the entire
DCC buffer.

Fixes: 5e8f6967b1 ("radv: add support for fast-clearing DCC layers on GFX9+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8443>
2021-01-13 08:33:40 +01:00
Bas Nieuwenhuizen
9a937330ef radeonsi: Only set modifier creation function for GFX9+ & with kernel support.
Fixes: c786150dfa ("radeonsi: Add modifier support.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3963
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8407>
2021-01-12 23:47:09 +00:00
Bas Nieuwenhuizen
4956f6d0bf radv: Add Android module info to linker script.
The Android Vulkan loader needs this symbol, so the addition of the
linker script broke Vulkan for Android.

(For non-Android builds: I checked that having a non-existent symbol in
 the linker script works ok and doesn't put the symbol in the library)

Fixes: 41bb6459d3 ("radv: restrict exported symbols with static llvm")
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8437>
2021-01-12 20:17:52 +00:00
Timur Kristóf
4ee6d68d1f aco: Wait for stores when NGG or legacy VS can finish early.
When there are no param exports in an NGG (or legacy VS) shader,
the NO_PC_EXPORT=1 is set, which means PS waves can launch before
the current stage finishes.

If the current stage has any stores, we need to make sure to wait for
those before we allow PS waves to start, so that PS can read what
these instructions stored.

Fossil DB results on Navi 10:
Totals from 45 (0.03% of 136420) affected shaders:
CodeSize: 87224 -> 87404 (+0.21%)
Instrs: 16750 -> 16795 (+0.27%)
Cycles: 69580 -> 69760 (+0.26%)
VMEM: 8022 -> 8167 (+1.81%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7868>
2021-01-12 16:43:27 +00:00
Timur Kristóf
38da379b3e aco: Note if rasterization can start early.
When there are no param exports in an NGG (or legacy VS) shader,
the NO_PC_EXPORT=1 is set by RADV, which means PS waves can launch
before the current stage finishes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7868>
2021-01-12 16:43:27 +00:00
Daniel Schürmann
00cf077c15 aco/ra: fix infinite recursion in get_reg_simple() with subdword registers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

Fixes: f8c7661eca ('aco: try to better align 8+ dword SGPR vectors')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Daniel Schürmann
7b669ff789 aco: simplify and fix operand/definition sizes
These are mainly needed for constant propagation
and subdword register allocation.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Daniel Schürmann
d495a5c183 radv: enable .lower_ineg
We already emit ineg as isub most of the time.

The results are a bit mixed, but shouldn't really make a difference.
A couple of additional copies are needed as isub writes scc.

Totals from 5975 (4.29% of 139391) affected shaders:
CodeSize: 31508648 -> 31509264 (+0.00%); split: -0.00%, +0.00%
Instrs: 6073379 -> 6073531 (+0.00%); split: -0.00%, +0.00%
Cycles: 47186280 -> 47187116 (+0.00%); split: -0.00%, +0.00%
VMEM: 2528515 -> 2529139 (+0.02%); split: +0.03%, -0.01%
SMEM: 596842 -> 596924 (+0.01%); split: +0.02%, -0.00%
SClause: 280596 -> 280594 (-0.00%)
Copies: 288554 -> 288669 (+0.04%); split: -0.00%, +0.04%
PreSGPRs: 240390 -> 240397 (+0.00%)
PreVGPRs: 349630 -> 349749 (+0.03%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Daniel Schürmann
e92bd57008 radv: don't lower_pack() after load-store-vectorization
Totals from 7 (0.01% of 139391) affected shaders:
CodeSize: 282900 -> 283324 (+0.15%); split: -0.01%, +0.16%
Instrs: 45287 -> 45338 (+0.11%); split: -0.01%, +0.12%
Cycles: 11496332 -> 11510396 (+0.12%); split: -0.00%, +0.12%
VMEM: 2355 -> 2335 (-0.85%)
Copies: 15506 -> 15561 (+0.35%)

A bit of noise in some parallel-rdp shaders.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Daniel Schürmann
987a0e6a67 radv: call nir_opt_algebraic_late() after lowering idiv for small bitsizes
This is needed because lower_idiv() introduces ineg again
which we'll remove next.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Daniel Schürmann
1ab9dd22a2 radv: optimize idiv_const for small bitsizes
No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Samuel Pitoiset
20af07d089 radv: fix color resolves if the dest image has DCC
Using the graphics resolve path when DCC is enabled should only be
a hint to avoid DCC fixup.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3388
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
2021-01-12 16:03:36 +00:00
Samuel Pitoiset
3e781056b9 radv: fixup DCC after color resolves using the compute path
If the dest image has DCC it should be re-initialized to the
uncompressed state.

Note that the driver always selects the graphics path if the dest
image has DCC, so this has no effect for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
2021-01-12 16:03:36 +00:00
Samuel Pitoiset
1f548b7670 radv: decompress DCC for partial resolves using the compute path
Because DCC is re-initialized to the uncompressed state after the
resolve, so if the app does a partial resolve it should be
decompressed first.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
2021-01-12 16:03:36 +00:00
Samuel Pitoiset
095a428844 radv: set depth to 1 for subpass resolves using the compute path
To match Vulkan convention.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
2021-01-12 16:03:36 +00:00
Rhys Perry
04e3d7ad93 aco: improve nir_op_vec with constant operands
Could still be improved a little. For example, 8-bit pack without
constants could be:
(s_pack_ll(x, z) & 0x00ff00ff) | ((s_pack_ll(y, w) & 0x00ff00ff) << 8)

fossil-db (Sienna):
Totals from 136 (0.10% of 139391) affected shaders:
CodeSize: 279776 -> 278144 (-0.58%)
Instrs: 50742 -> 50470 (-0.54%)
Cycles: 211560 -> 210472 (-0.51%)
SMEM: 3607 -> 3557 (-1.39%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8421>
2021-01-12 15:50:54 +00:00
Rhys Perry
255ca7ecda radv: set invariantgeom for Shadow of the Tomb Raider
Work around flickering foliage on GFX10.3

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4064
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8104>
2021-01-12 15:11:49 +00:00
Rhys Perry
f17de6a803 radv: add RADV_DEBUG=invariantgeom
This can be used to work around a common class of bugs appearing as
flickering.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8104>
2021-01-12 15:11:49 +00:00
Samuel Pitoiset
c24d6916e6 aco: fix inserting expcnt for MIMG on GFX6
MIMG VDATA has moved to its own operand.

Fixes: 962c917cea ("aco: move MIMG VDATA to its own operand")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8435>
2021-01-12 11:32:12 +00:00
Daniel Schürmann
bd8e84eb8d nir: replace .lower_sub with .has_fsub and .has_isub
This allows a more fine-grained control about whether
a backend supports one of these instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6597>
2021-01-11 19:13:51 +00:00
Samuel Pitoiset
d2524ed4a0 radv: mark VK_IMAGE_CREATE_SPARSE_RESIDENCY_BIT as unsupported on GFX6-7
This is only supported on GFX8+, this fixes a ton of CTS failures
on my Pitcairn (GFX6).

Fixes: af7fb4df50 ("radv: Add sparse image queries.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8415>
2021-01-11 17:17:42 +00:00
Rhys Perry
4ea0ce2f55 aco: remove can_reorder semantic in get_sync_info_with_hack
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8416>
2021-01-11 16:35:19 +00:00
Rhys Perry
f8c7661eca aco: try to better align 8+ dword SGPR vectors
This doesn't have much of an effect, but it helps avoid a
pathological case for Assassin's Creed Valhalla and a RDR2 shader with a
future change.

fossil-db (Sienna):
Totals from 55074 (39.51% of 139391) affected shaders:
SGPRs: 3515076 -> 3567744 (+1.50%); split: -0.01%, +1.51%
CodeSize: 206942120 -> 206941868 (-0.00%); split: -0.00%, +0.00%
Instrs: 39625900 -> 39625837 (-0.00%); split: -0.00%, +0.00%
Cycles: 1640088780 -> 1640088828 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4070
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8416>
2021-01-11 16:35:19 +00:00