No driver supports urol/uror on all bit sizes. Intel gen11+ only for 16
and 32 bit, Nvidia GV100+ only for 32 bit. Etnaviv can support it on 8,
16 and 32 bit.
Also turn the `lower` into a `has` option as only two drivers actually
support `uror` and `urol` at this momemt.
Fixes crashes with CL integer_rotate on iris and nouveau since we emit
urol for `rotate`.
v2: always lower 64 bit
Fixes: fe0965afa6 ("spirv: Don't use libclc for rotate")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by (Intel and nir): Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27090>
(cherry picked from commit f2b7c4ce29)
Previous commit upreved deqp only for the Android
Fixes: 1ff4687e86 ("ci: uprev deqp-runner from 0.16.1 to 0.18.0")
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
[Eric]
- rename the deqp-runner version to DEQP_RUNNER_VERSION instead of DEQP_VERSION
- update image tags
- fix expectations lists
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27062>
(cherry picked from commit 4ff77f08e4)
If Mesa is executed under valgrind, fd_bo_init_common() calls
fd_bo_map() internally. For the heap (sub-block) allocator this causes a
segfault in fd_bo_map(), when this function tries to call the offset()
callback.
To prevent this from happening, preallocate fb->map before calling into
fd_bo_init_common(), stop calling VG_BO_ALLOC() if the memory map is
already initialised and disable the VG_BO_FREE call for the heap
allocator.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26277>
If the shader memory has been allocated with the FD_BO_NOMAP and got
later allocated a memory chunk during fd_bo_upload(), this can result in
the valgrind splat when it tries to release the free and/or cache the
BO. To fix this issue, notify valgrind about newly mmaped shader memory.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26277>
Partially revert the commit f4c9e9329c ("ir3/a6xx: Fix immediate
offset stg/ldg path").
There is no need to multiply the immediate offsets by 4. Doing so
results in loading and/or storing the data at wrong locations.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26817>
A690 seem to have broken UBWC for depth/stencil, it requires
depth flushing where we cannot realistically place it, like between
ordinary draw calls writing read/depth. WSL blob seem to use ubwc
sometimes for depth/stencil.
Some tests that this fixes:
dEQP-VK.pipeline.monolithic.stencil.format.d24_unorm_s8_uint.states.fail_repl.pass_decw.dfail_inv.comp_never
dEQP-VK.api.image_clearing.core.partial_clear_depth_stencil_attachment.single_layer.d32_sfloat_s8_uint_separate_layouts_depth_64x11
dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_depth_stencil_attachment.single_layer.d16_unorm_33x128
dEQP-VK.glsl.builtin_var.fragdepth.point_list_d32_sfloat_s8_uint_no_depth_clamp
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26226>
While running tests, it is be useful to have non-sequenced dumps of
certain buffers to see their contents from changes in the decompiled
CS. This introduces a function gpu_read_into_file(...) for specifying
a file to read a specific GPU buffer into after replaying the CS.
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26465>
As most of the pkt values are arbitrarily encoded numbers, they are
less readable as integers and printing them as hex is preferable.
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26465>
In newer traces, in any cases where instructions need to be executed
for both cases of a predicate, such as for GMEM/sysmem. The proprietary
driver emits the TRUE and FALSE body one after another with a NOP at
the end of the TRUE condition body so the CP skips over the FALSE body.
Currently, the NOP skips over all instructions in the ELSE body which
results in them not being decoded whatsoever. This commit checks if
we encounter any NOPs while in a conditional block and appropriately
parses out them out into their own ELSE scope when we do.
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26465>
Due to the larger amount of conditional execution in newer traces
the flat view makes it hard to parse what might be conditionally
executed and what might now. This makes it easier to view by adding
a scope for conditionally executed commands which is indented to the
next level.
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26465>
Allow fd_bo_heap_alloc() to return NULL if the heap is exausted (or
fragmented) instead of segfaulting. Then handle the error properly in
bo_new().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26787>
In the case of a dedicated image allocation, stash the layout metadata
on the backing GEM object, so that when imported the metadata can be
retrieved in order to properly interpret the imported memobj.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25945>
Add a struct for communicating layout metadata between turnip and
gallium driver. For now, all that is needed is the modifier, but we
can extend it in the future if needed.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25945>
Add the `FARM: google` variable to the .google-freedreno-test job,
which is extended by devices managed by the Google farm. Add the
`FARM: collabora` variable to sc7180-trogdor-kingoftown,
sc7180-trogdor-lazor-limozeen and sm8350-hdk device types which
are available in Collabora farm.
This commit also adds DEVICE_TYPE variable for the .a306-test,
.a530-test and .a630-test jobs.
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25807>
This removes the last unknown flag from read/write instructions.
Because we now handle the write in CP_SET_DRAW_STATE more correctly when
emulating, we also have to update the control register definitions and
draw state emulation code to adjust.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
It seems like starting with a6xx, the SQE has a special register space
for reading/writing the state of the processor itself, mainly used for
saving/restoring its state in preemption. Add support for disassembling
it, removing one of the unknown flags bits.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
Turns out a5xx already had store, although not load. It was using the
high bit of the unknown flags for this.
Note that a6xx does use the high bit, and we fall back to not decoding
it at all here before properly decoding it in the next commit. Splitting
up the commits seems worth this small breakage.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
ir3_nir_lower_preamble cannot handle 64b @load/store_preamble so we have
to make sure ir3_nir_opt_preamble will never produce them. Up to now,
nir_lower_locals_to_regs was run after preamble lowering so 64b locals
could still be around when lowering the preamble. This patch moves
running this pass, as well as ir3_nir_lower_64b_regs, to before the
preamble lowering.
Fixed Piglit tests:
- spec@arb_gpu_shader_fp64@execution@fs-indirect-temp-double-dst
- spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-frexp-dvec4-variable-index
This patch has no impact on shader-db.
Note: a few cleanup passes used to be run after nir_lower_locals_to_regs
(nir_opt_algebraic, nir_opt_constant_folding) and after
ir3_nir_lower_64b_regs (nir_lower_alu_to_scalar, nir_copy_prop). As far
as I can tell, these are not necessary anymore when running the register
lowering earlier so this patch removes them.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26737>
After all int64/double lowerings, there might still be 64b registers
left which ir3 currently doesn't handle. This only happens in a small
number of Piglit tests where those registers (or the variables they come
from) did not get DCE'd.
This patch handles 64b registers in ir3 by adding a NIR pass that does
the following:
- @decl_reg -> split in two 32b ones
- @store_reg -> unpack_64_2x32_split_x/y and two separate stores
- @load_reg -> two separate loads and pack_64_2x32_split
After this pass, the 64b vecs used for the original loads/stores are
still present and are also not handled yet by ir3. This patch removes
them by running nir_lower_alu_to_scalar and nir_copy_prop.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26175>
Until gets figured out why 6.6 kernel is ~ 1 ‒ 5 minutes slower per run.
Acked-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26611>
