Commit graph

6118 commits

Author SHA1 Message Date
Lionel Landwerlin
28207669d0 anv: Fix stencil layout in render passes
We incorrectly utilize the stencil layouts structures even if we
should stick to the depth_stencil ones if the layout includes stencil.

v2: Don't forget stencil only layout (Nanley)
    Simplify callers of new helper functions (Nanley)

v3: Store VK_IMAGE_LAYOUT_UNDEFINED when no stencil is available (Nanley)
    Use a switch statement (Nanley)

v4: Consider all layouts but depth only to be potential stencil layouts (Lionel)

v5: Refactor helper in vk_image_layout_depth_only() and discard
    VkAttachmentDescriptionStencilLayoutKHR in
    VkAttachmentDescription2KHR if format is not depth/stencil.

v5: s/LAYOUT_COLOR_ATTACHMENT_OPTIMAL/LAYOUT_DEPTH_ATTACHMENT_OPTIMAL/ (Nanley)

v6: Fix overly harsh assert()

Fixes: c1c346f166 ("anv: implement VK_KHR_separate_depth_stencil_layouts")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4084
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8475>
2021-01-20 20:36:34 +00:00
Caio Marcelo de Oliveira Filho
77aa86a521 intel/fs: Separate SLM size calculation from encoding
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8486>
2021-01-19 21:49:04 +00:00
Abhishek Kumar
276e3927b5 intel: change urb max shader geometry for CML GT1
Below deqp cts failure is seen on CML GT1 only , GT2 all test
passes, changing the max shader geometry to 256 (previous 640)
fixes all failure tests.Similar issue on BDW GT1
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3173

dEQP-GLES31.functional.geometry_shading.layered.
		render_with_default_layer_cubemap
		render_with_default_layer_3d
		render_with_default_layer_2d_array

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4102

Signed-off-by: Abhishek Kumar <abhishek4.kumar@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8550>
2021-01-19 13:37:35 +00:00
Jason Ekstrand
63a431b81c anv: Add a trivial implementation of VK_KHR_deferred_host_operation
This isn't actually capable of deferring anything; it just trivially
returns success.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7735>
2021-01-18 10:09:51 -06:00
Lionel Landwerlin
9a54aa131e intel/perf: move gt_frequency to results
We want to unify things a bit between GL & Vulkan. So store those
values in the results rather than just in the GL query code.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
b7032d6776 intel/perf: link queries back to the gen_perf_config object
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
e79f112e4f intel/perf: add definition for generic perf counters
Those are not part of the OA report but will be used in upcoming
counters.

v2: Rename counter defines (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
bd7df91372 intel/perf: restructure i915 perf version checks
Trying to make things more readable.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
d8154c4006 intel/mi_builder: fix self modifying batches
So far we only write a maximum of 4 dwords further into the batch and
it seems just going over the CS prefetch was enough.

Turns out writing more dwords can delay the writes and we start
prefetching stuff that hasn't landed in memory yet.

This fixes the issue by stalling the CS to ensure the writes have
landed before we go over the prefetch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 796fccce63 ("intel/mi-builder: add framework for self modifying batches")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
359312ae01 intel/mi_builder: optimize 64bit immediate register loads & memory stores
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:23 +02:00
Lionel Landwerlin
dbeca67a1d anv: don't disable KHR_performance_query in debug mode
This is useful to verify that queries are built properly and avoiding
to deal with i915-perf (typically under simulation).

v2: Remove likely() (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
2021-01-15 13:26:22 +02:00
Lionel Landwerlin
d4b4d69d4d anv: add transfer usage for color/depth/stencil attachments
We sometimes use anv_layout_to_aux_state() to compute the aux state of
an image during the resolve operations at the end of a render
(sub)pass.

If we're dealing with a multisampled image that is created without a
transfer usage, our internal code might trigger a resolve using the
transfer layout (see genX_cmd_buffer.c:cmd_buffer_end_subpass), for
which the image doesn't the usage bit. The current code tries to AND
the 2 usages which won't have any bit in common, thus skipping all
checks below.

v2: Add the transfer usages depending on attachment usage (Lionel)

v3: Limit to samples > 1 (Jason) && DEPTH_STENCIL_ATTACHMENT_BIT (Lionel)

v4: Add transfer usage at image creation (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 54b525caf0 ("anv: Rework anv_layout_to_aux_state")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4037
Reviewed-by: Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8307>
2021-01-14 09:51:31 +02:00
Jason Ekstrand
f4902bb189 intel/genxml,anv,iris: Drop the legacy compute path from gen125.xml
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jason Ekstrand
8f85e68dea anv: Enable push constants on gen12-hp
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jason Ekstrand
369eab9420 intel/fs: Emit code for Gen12-HP indirect compute data
Reworks:
 * Jordan: Apply to gen > 12
 * Jordan: Adjust comment about loading constants

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jason Ekstrand
4077ca1cc8 anv: Add a general state pool
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jordan Justen
a6f8d59142 anv: Use COMPUTE_WALKER for gen12-hp
Rework: Rafael Antognolli, Jason Ekstrand
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:28 -08:00
Jordan Justen
91fe96cfbe anv: Don't use MEDIA_INTERFACE_DESCRIPTOR_LOAD for gen12-hp
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jordan Justen
435b272241 anv: Emit CFE_STATE for gen12-hp
Rework:
 * make scratch TODO. (Jason)
 * emit_compute_cs_state => emit_compute_state. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jason Ekstrand
b4ffbf1521 intel/fs: Allow compute dispatch without a pushed subgroup ID on Gen12-HP
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jordan Justen
9294193098 intel/compiler: Disable push constants on gen12-hp
We currently don't use push constants with the COMPUTE_WALKER command.
Make all uniforms to be pull constants.

The local group id previously was a push constant, but is now
available in R0.2[7:0].

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jason Ekstrand
b7c1ad00fc intel/tools: Decode COMPUTE_WALKER
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jordan Justen
cdc9e22a3a intel/genxml/gen125: Add CFE_STATE and COMPUTE_WALKER
Reworks:
 * Jason: Captalize COMPUTE_WALKER::BTD mode
 * Jason: Make COMPUTE_WALKER::InlineData an array
 * Jason: Remove stale fields, uint=>bool, add missing enum values.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
2021-01-13 13:10:27 -08:00
Jordan Justen
231c27adaf intel/common: Build mi_builder_test for gen 12.5
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8424>
2021-01-11 13:05:49 -08:00
Daniel Schürmann
bd8e84eb8d nir: replace .lower_sub with .has_fsub and .has_isub
This allows a more fine-grained control about whether
a backend supports one of these instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6597>
2021-01-11 19:13:51 +00:00
Erico Nunes
faaba0d6af nir/lower_vec_to_movs: don't vectorize unsupports ops
If the instruction being coalesced would be vectorized but the target
doesn't support vectorizing that op, skip coalescing.
Reuse the callbacks from alu_to_scalar to describe which ops should not
be vectorized.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6506>
2021-01-11 13:13:30 +00:00
Jason Ekstrand
2d08711a2c anv: Bump maxGeometryInputComponents to 128 on Gen8+
See 8e627af59d and 1e3e72e305 for why this may not be a good
idea on Gen7.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8397>
2021-01-08 23:17:26 +00:00
Rhys Perry
f199b7188b nir/load_store_vectorize: add data as callback args
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>
2021-01-07 16:34:53 +00:00
Rhys Perry
00c8bec47b nir: add nir_load_store_vectorize_options
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>
2021-01-07 16:34:53 +00:00
Michel Dänzer
1de2fd0cf2 wsi/x11: Always link against xcb-xrandr
The next commit will make use of it even without
VK_USE_PLATFORM_XLIB_XRANDR_EXT.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>
2021-01-07 14:57:45 +01:00
Christian Gmeiner
23c963f11b anv: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
2021-01-06 14:34:41 +00:00
Christian Gmeiner
c5a9270109 intel/compiler: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
2021-01-06 14:34:41 +00:00
Christian Gmeiner
fc3ce00791 intel/blorp: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
2021-01-06 14:34:41 +00:00
Dave Airlie
5692e2dda5 intel/isl: move get_tile dims/masks to common isl header
Both classic and iris have the same code for this, but none of it
is dependent on drivers, so just add inline helpers to isl.

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8253>
2020-12-30 06:06:33 +10:00
Yevhenii Kolesnikov
5ad54d498c intel/fs: don't spill a register, set by undef
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3941
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8185>
2020-12-21 21:18:01 +00:00
Michael Forney
434da21a7c meson: add missing dependency on generated git_sha1.h
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8121>
2020-12-17 00:03:22 +00:00
Robin Ole Heinemann
df76963a5c anv: Add DRM_RDWR flag in anv_gem_handle_to_fd
The DRM_RDWR flag is needed for mmap with PROT_WRITE to work.

Cc: mesa-stable
Signed-off-by: Robin Ole Heinemann <robin.ole.heinemann@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8075>
2020-12-15 08:20:34 +00:00
Vinson Lee
56cb5cf34e intel/genxml: Avoid generating identical 12.5 and 12 branches.
Fix defects reported by Coverity Scan.

Identical code for different branches (IDENTICAL_BRANCHES)

identical_branches: The same code is executed regardless of
whether 0 is true, because the 'then' and 'else' branches are
identical. Should one of the branches be modified, or the entire
'if' statement replaced?

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8001>
2020-12-12 02:36:20 +00:00
Nanley Chery
574429f952 intel/blorp: Drop support for STC_CCS resolves
There are no users of this feature.

Reverts the following commits:

* 87c57b8dae (effectively)
* 53d472df24
* 9ab0e92cff

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8021>
2020-12-10 22:41:33 +00:00
Tapani Pälli
5998a6543a anv: fix calculation of buffer size in case dynamic size is used
VK spec got clarification about the pSizes parameter.

Fixes set of new tests:
   dEQP-VK.pipeline.extended_dynamic_state*with_offset*

v2: move offset subtract to be part of size calculation (Jason)

CC: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3871
Fixes: b9a05447a1 ("anv: dynamic vertex input binding stride and size support")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7439>
2020-12-10 08:26:34 +02:00
Marcin Ślusarz
aff845da67 intel/tools/aubinator_error_decode: fix small memory leaks
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7994>
2020-12-09 12:15:56 +00:00
Marcin Ślusarz
00cd3f7d13 intel/tools/aubinator_error_decode: cleanup path/file handling
Should help some compilers/static analyzers understand this code and avoid
things like this:

../src/intel/tools/aubinator_error_decode.c:850:19: warning: "path" may be used uninitialized in this function [-Wmaybe-uninitialized]
  850 |             ret = asprintf(&filename, "%s/%d/i915_error_state", path, minor);

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7994>
2020-12-09 12:15:56 +00:00
Lionel Landwerlin
87ad5f5b0d isl: Fix android build
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Mauro Rossi <issor.oruam@gmail.com>
Fixes: f08d8c849e ("intel/isl: Build gen 12.5")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3931
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7938>
2020-12-05 11:42:15 +00:00
Caio Marcelo de Oliveira Filho
0a7abee60b anv: Avoid a couple of warnings related to vk_error macros
When DEBUG is not defined, no error reporting is done, the error is
just returned back.  The current definition a couple of warnings in
anv_formats.c.  First when the return value is intentionally ignored

  ../src/intel/vulkan/anv_formats.c:989:48: warning: statement with no effect [-Wunused-value]
    989 |          vk_errorfi(instance, physical_device, VK_ERROR_FORMAT_NOT_SUPPORTED,
        |                                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  ../src/intel/vulkan/anv_private.h:486:55: note: in definition of macro ‘vk_errorfi’
    486 | #define vk_errorfi(instance, obj, error, format, ...) error
        |                                                       ^~~~~

and also when an argument is used only

  ../src/intel/vulkan/anv_formats.c:908:25: warning: unused variable ‘instance’ [-Wunused-variable]
    908 |    struct anv_instance *instance = physical_device->instance;
        |                         ^~~~~~~~
  ../src/intel/vulkan/anv_formats.c: In function ‘anv_GetPhysicalDeviceImageFormatProperties2’:
  ../src/intel/vulkan/anv_formats.c:1231:25: warning: unused variable ‘instance’ [-Wunused-variable]
   1231 |    struct anv_instance *instance = physical_device->instance;
        |                         ^~~~~~~~

to avoid both issues, use a static inline function that just returns
it's argument but can consume other input. Ignoring the return value
of a function is OK, and the extra input can be tagged as UNUSED
getting rid of both warnings.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7860>
2020-12-02 08:30:46 -09:00
Jason Ekstrand
a1976e1cb2 intel/fs: Implement nir_jump_halt
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5071>
2020-12-01 16:19:18 -06:00
Jason Ekstrand
6992d2f625 intel/fs: Emit HALT_TARGET in emit_nir_code()
Instead of making it a fragment-specific thing based on uses_kill, track
whether or not we need one in fs_visitor and emit HALT_TARGET at the end
of emit_nir_code() if needed.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5071>
2020-12-01 16:19:14 -06:00
Jason Ekstrand
4a7f0aa2e0 intel/fs: Remove unnecessary HALT_TARGET in opt_redundant_halt()
This means the pass has to walk all the instructions but it was doing
that in a bunch of cases anyway when it didn't have a HALT_TARGET.
However, removing HALT_TARGET frees up the scheduler a bit because
HALT_TARGET is considered a scheduling barrier.  The shader-db results
are kind-of a wash but we're about to add HALT_TARGET unconditionally so
we want to be able to get rid of it.

Shader-db results on Ice Lake:

    total instructions in shared programs: 19935623 -> 19935623 (0.00%)
    instructions in affected programs: 0 -> 0
    helped: 0
    HURT: 0

    total cycles in shared programs: 976758472 -> 976766135 (<.01%)
    cycles in affected programs: 11097707 -> 11105370 (0.07%)
    helped: 1750
    HURT: 875
    helped stats (abs) min: 1 max: 866 x̄: 26.39 x̃: 4
    helped stats (rel) min: <.01% max: 39.24% x̄: 1.25% x̃: 0.46%
    HURT stats (abs)   min: 1 max: 1678 x̄: 61.54 x̃: 10
    HURT stats (rel)   min: <.01% max: 65.69% x̄: 1.86% x̃: 0.42%
    95% mean confidence interval for cycles value: -2.48 8.32
    95% mean confidence interval for cycles %-change: -0.40% -0.03%
    Inconclusive result (value mean confidence interval includes 0).

    LOST:   62
    GAINED: 46

All of the lost/gained programs are SIMD32 fragment shaders.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5071>
2020-12-01 16:19:10 -06:00
Jason Ekstrand
f9d549b2bf intel/fs: Use BRW_OPCODE_HALT for discards
We're about to start using it to implement nir_jump_halt which has
nothing inherently to do with fragment shaders or discards.  May as well
name it for the HW instruction it generates.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5071>
2020-12-01 16:19:08 -06:00
Jason Ekstrand
e76e359007 intel/fs: Rename PLACEHOLDER_HALT to HALT_TARGET
It's a bit more explicit and will play more nicely with what we're about
to do.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5071>
2020-12-01 16:18:50 -06:00
Jordan Justen
071fd55381 intel/compiler: Add GEN125 to enum gen
Recommended-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7757>
2020-12-01 19:06:22 +00:00