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intel/blorp: Set stencil resolve enable bit

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When set, the stencil buffer is filled with the true stencil values and
we have to disable stencil buffer clear enable bit.

v2: 1) Refactor code little bit (Nanley Chery)
    2) Fix assertion (Nanley Chery)

v3: 1) Remove unncessary assignment (Nanley Chery)
    2) Fix GEN_GEN check (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
This commit is contained in:
Sagar Ghuge 2019-09-17 11:04:15 -07:00
parent c401186762
commit 87c57b8dae
1 changed files with 17 additions and 4 deletions
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21
src/intel/blorp/blorp_genX_exec.h
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@ -1636,11 +1636,18 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
*/
assert(params->depth.enabled || params->stencil.enabled);
/* The stencil buffer should only be enabled if a fast clear operation is
* requested.
/* The stencil buffer should only be enabled on GEN == 12, if a fast clear
* or full resolve operation is requested. On rest of the GEN, if a fast
* clear operation is requested.
*/
if (params->stencil.enabled)
if (params->stencil.enabled) {
#if GEN_GEN >= 12
assert(params->hiz_op == ISL_AUX_OP_FAST_CLEAR ||
params->hiz_op == ISL_AUX_OP_FULL_RESOLVE);
#else
assert(params->hiz_op == ISL_AUX_OP_FAST_CLEAR);
#endif
}
/* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
*
@ -1696,7 +1703,13 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
break;
case ISL_AUX_OP_FULL_RESOLVE:
assert(params->full_surface_hiz_op);
hzp.DepthBufferResolveEnable = true;
hzp.DepthBufferResolveEnable = params->depth.enabled;
#if GEN_GEN >= 12
if (params->stencil.enabled) {
assert(params->stencil.aux_usage == ISL_AUX_USAGE_CCS_E);
hzp.StencilBufferResolveEnable = true;
}
#endif
break;
case ISL_AUX_OP_AMBIGUATE:
assert(params->full_surface_hiz_op);