Xe2 platforms have a different way to disable CCS
compression.
Suggested by Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37098>
This helps us to catch a compressed bo is picked up for
an uncompressed modifiers when importing dmabuf, and vise
versa.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37098>
For an image created either without a modifier to share or as the
destination image to get rid of compression by re-allocation, it
should have compression disabled.
Close: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13729
(Fix firefox misrendering when gfx.wayland.hdr option is true)
Backport-to: 25.2
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37098>
If no external/llvm-project directory is present, build with SwiftShader’s
static LLVM library if available. This can simplify Mesa builds inside
AOSP.
Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com>
Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37607>
If the (NIR) destination is a register (i.e., not an SSA value), the
destination of the BRW instruction will not be is_scalar. This occurs in
some shaders in Final Fantasy XVI (and
finalfantasytype0_1.rdc.2826e29da3722a83.1.foz).
If the destination is not is_scalar, revert most of this code to the
state previous to f3593df877. This means
- Allocate a SIMD1 register and UNDEF it.
- Emit a SIMD1 MOV_RELOC_IMM to that register.
- Emit an additional MOV to expand the SIMD1 result.
Closes: #12520
Fixes: f3593df877 ("brw/nir: Treat load_reloc_const_intel as convergent")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37384>
MR !36998 / commit 72f2565fc9 introduced
an issue where QueryDeviceInfo is not called in eglQueryDeviceBinaryEXT,
which causes the queried UUID to always be zero.
This commit fixes the issue by adding a call to QueryDeviceInfo.
Also, it refactors the inconsistent function names passed to _eglError.
Signed-off-by: Christoph Neuhauser <christoph.neuhauser@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37616>
According to the comment removing non host visible heaps
was only meant for non-ReBAR. We can detect ReBAR and
allow host image copy on non host visible heaps.
Also drops an old comment from the first rudimentary
implementation of this function.
Results for *host_image_copy* on a Ada gpu with ReBAR.
Test run totals:
Passed: 51686/149362 (34.6%)
Failed: 0/149362 (0.0%)
Not supported: 97676/149362 (65.4%)
Warnings: 0/149362 (0.0%)
Waived: 0/149362 (0.0%)
Reviewed-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37385>
The host copy logic doesn't support unpacking/packing D24X8, and if we
were to support it, it would be inefficient because of the non-32-bit
alignment. Given host copy is not a thing on AFBC resources, and given
the Z24_UNORM_PACKED is mostly beneficial to AFBC(Z) resources, let's
restrict its use to this case only and use Z24X8 otherwise.
Fixes: a620f33b7c ("panvk: Add planar Z24S8 support")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37473>
We need to split dual-aspect copies into separate copies.
Fixes: a620f33b7c ("panvk: Add planar Z24S8 support")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Tested-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37473>
Switch cases should align with the switch() statement.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Tested-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37473>
VK_KHR_maintenance8 allows such copies, but there are a few things we
need to fix to support the case where the destination and source aspects
don't match.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Tested-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37473>
The decoder has been broken for years. It creates 3-plane video
buffer with RGB16 format for all three planes, which hasn't been
working since 243475b96c.
It also doesn't make sense anymore to use shader decoder for a codec
this old.
Acked-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37507>
- Implement load_interpolated_input and friends.
- Optimize load_barycentric_* cases that can be simplified.
- Initial support for non-standard sample locations.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37540>
Without this, somebody trying to map a buffer for write by the CPU would
fail. This is not common to do in hardware driver environments, but it
shouldn't be disallowed, and there's no downside to allowing it.
I did skip virgl, because that's one where I don't know for sure if there
wouldn't be a downside to allowing RDWR (there are other virt exports
where RDWR is gated on a mappable flag).
This is a follow-up to !37088 to keep copy and paste from introducing the
same bug anywhere else.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37339>
This is required for OpenCL but not Vulkan. This fixes a bunch of
OpenCL CTS fails using the SPIR-V back-end in LLVM as opposed to
SPIRV-LLVM-Translator.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37555>
on sm70+ where we don't have a native bfe instruction. This
implementation is fewer instructions than the nir lowering.
This also implements the bfe semantics that vkd3d-proton wants. d3d12
wants specific behavior for out-of-bounds ibfe like
bitfieldExtract(-1, 15, 20) while spirv considers this undefined
behavior. Tested with VKD3D_TEST_FILTER=test_shader_instructions
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13795
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37592>
In case of a unbound subchannel usage, the hardware will route it to the
GPFIFO class.
NVIDIA blobs use this and this was causing an assertion to be fired up
in nv_push_dump.
This adds support for that and also add mapping for cls_gpfifo in
nv_push_dump.
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37475>
From nvidia-open-kernel-modules as they missing on open-gpu-doc at the
moment.
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37475>
If a given generation hasn't removed any methods, then the default case
can defer to the previous generation without changing the output at all.
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37475>
Note that this changes the output so it lists the method as being in the
class where it most recently changed rather than always in the class of
the running gpu. Personally, I find this more useful than the old
behavior.
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37475>
