Commit graph

112638 commits

Author SHA1 Message Date
Dave Airlie
69ff738eb0 draw: add support for ssbo ptrs to jit tables.
This adds ssbo/num_ssbo ptrs to the vs/gs jit tables.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-07 16:23:46 +10:00
Dave Airlie
e84570ba70 gallivm: add some basic SSBO limits. (v2)
v2: update ssbo size

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-07 16:23:44 +10:00
Dave Airlie
7c3807c1b3 util: add util_copy_shader_buffer.
This just adds an inline to copy a pipe_shader_buffer.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-07 16:23:40 +10:00
Dave Airlie
5ff697aa65 gallivm: add ssbo pointers to the soa build api.
Need to pass ssbo + ssbo size pointers just like constants.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-07 16:23:36 +10:00
Dave Airlie
2a55acbc1d gallivm: add compare exchange wrapper
This just pulls the wrapper from LLVM for older versions

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-07 16:23:32 +10:00
Dave Airlie
4f709c86a9 vertex shader: add exec masking (v2)
As suggested by Roland this is just a compare of fetch_max
vs the counter, much simpler than my original spaghetti code.

We require the vertex shader to have an exec mask to get proper
ssbo/image load/atore/atomics semantics

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-07 16:23:27 +10:00
Alexandros Frantzis
4271430dd7 virgl: Hide internal virgl_resource functions
Since the transition to virgl_resource_transfer_map(), several
previously public virgl_resource functions are not required to be public
anymore.

We also move the functions earlier in the file so they can be used
without functions declarations.

Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-07-06 19:30:38 -07:00
Alexandros Frantzis
e5b54d0018 virgl: Use virgl_resource_transfer_map for textures
Replace custom texture map code (for maps which don't require resolve)
with virgl_resource_transfer_map.

Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-07-06 19:30:37 -07:00
Alexandros Frantzis
f8975f8f2f virgl: Use virgl_resource_transfer_map for buffers
Replace custom buffer map code with virgl_resource_transfer_map.

Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-07-06 19:30:34 -07:00
Alexandros Frantzis
bb0a38d819 virgl: Introduce virgl_resource_transfer_map
Normal mapping of buffers and textures uses almost identical logic.
This commit extracts the this logic in the form of the
virgl_resource_transfer_map() helper function.

Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-07-06 19:30:22 -07:00
Jason Ekstrand
4633298fd6 iris: Use a uint16_t for key sizes
sizeof(struct brw_vs_prog_key) == 324.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-04 19:52:34 -05:00
Marek Olšák
aa5dab27f9 ac: destroy passes in ac_destroy_llvm_compiler
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-04 15:39:04 -04:00
Marek Olšák
ea64d66fde ac: use an LLVM fence instead of s.waitcnt when possible
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-04 15:39:03 -04:00
Marek Olšák
14450c8c41 ac: remove unused AC_WAIT_EXP
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-04 15:39:01 -04:00
Marek Olšák
fe5dbe75b2 ac: only set ac_dlc in ac_llvm_build.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-04 15:39:00 -04:00
Marek Olšák
8a71f60194 ac: replace glc,slc with cache_policy for loads
cosmetic change

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-04 15:38:56 -04:00
Marek Olšák
a29e781961 ac: replace glc,slc with cache_policy for stores
cosmetic change

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-04 15:38:54 -04:00
Jonathan Marek
5feb8adb0f etnaviv: implement buffer compression
Vivante GPUs have lossless buffer compression using the tile-status bits,
which can reduce memory access and thus improve performance.

This patch only enables compression for "V4" compression GPUs, but the
implementation is tested on GC2000(V1) and GC3000(V2). V1/V2 compresssion
looks absolutely useless, so it is not enabled.

I couldn't test if this patch breaks MSAA, because it looks like MSAA is
already broken.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:05:18 -04:00
Jonathan Marek
f6a0d17abe etnaviv: detect v4 compression
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:05:18 -04:00
Jonathan Marek
e910acb3f2 etnaviv: rs: don't use etna_compatible_rs_format when possible
This mirrors the change in blt. RS cares about this for msaa/compression.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:05:18 -04:00
Jonathan Marek
66411521ea etnaviv: combine translate_ts_sampler_format/translate_msaa_format
Both translate the same thing, so just add the missing cases into one.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:05:18 -04:00
Jonathan Marek
84c87f40fb etnaviv: fix compression format not set correctly in TS_MEM_CONFIG
VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT() needs to be used.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:05:18 -04:00
Jonathan Marek
53475c85fd etnaviv: set correct ts_clear_value for BLT engine
BLT engine uses all ones to clear TS, set ts_clear_value to match that.
Note: ts_clear_value is never used with BLT engine.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:05:18 -04:00
Jonathan Marek
7c7eaaed4a etnaviv: remove initial CPU ts clear
Since we have "ts_valid" to avoid using uncleared ts, this memset serves
no purpose. Also it is broken because it doesn't use cpu_prep/cpu_fini.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:05:18 -04:00
Jonathan Marek
95d937852e etnaviv: implement TS_MODE for GC7000L
GC7000L has a TS mode with larger tiles, which improves performance.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:05:18 -04:00
Jonathan Marek
bc5ae6a330 etnaviv: fix ts size calculation
The size of the TS is screen->specs.bits_per_tile bits per tile, with each
tile being 64 bytes of the resource.

This gives the same result for 32bpp formats, but reduces the size of TS
for 16bpp formats by 2.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:05:09 -04:00
Jonathan Marek
2f540745ad etnaviv: update headers from rnndb
Update to etna_viv commit 8a8b13a and use new names in the code.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-07-04 14:04:47 -04:00
Eric Engestrom
c314ba2c26 scons: s/HAVE_NO_AUTOCONF/HAVE_SCONS/
Back when autotools and scons were the two build systems, it kinda made
sense to call scons "not autoconf", but autoconf's been gone for a while
now and other build systems have been added (android.mk and meson), so
the name really doesn't make any sense anymore.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-04 16:41:23 +01:00
Bas Nieuwenhuizen
bbbcb49f9b radeonsi: Fix some warnings.
../mesa/src/gallium/drivers/radeonsi/si_compute_blit.c: In function ‘si_clear_buffer’:
../mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:195:11: warning: unused variable ‘clear_alignment’ [-Wunused-variable]
  unsigned clear_alignment = MIN2(clear_value_size, 4);
           ^~~~~~~~~~~~~~~
[23/60] Compiling C object 'src/gallium/drivers/radeonsi/3cdc30e@@radeonsi@sta/si_compute_prim_discard.c.o'.
../mesa/src/gallium/drivers/radeonsi/si_compute_prim_discard.c: In function ‘si_prepare_prim_discard_or_split_draw’:
../mesa/src/gallium/drivers/radeonsi/si_compute_prim_discard.c:1106:7: warning: unused variable ‘compute_has_space’ [-Wunused-variable]
  bool compute_has_space = sctx->ws->cs_check_space(cs, need_compute_dw, false);

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-04 11:12:27 +00:00
Nicolai Hähnle
cb07f91489 amd/common: move ac_shader_{binary,reloc} into r600 and rename
They are no longer used by radeonsi or radv.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-04 10:52:26 +00:00
Nicolai Hähnle
510e74ff48 amd/common: removed unused ac_shader_binary functions
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-04 10:52:26 +00:00
Nicolai Hähnle
b398230e6d amd/common: remove unused ac_compile_module_to_binary
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
6a220e67ce radv: Switch to using rtld.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
5ff651c0a7 radv: Move more stuff to variant create time.
Due to them depending on the linker result.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
726a31df70 radv: Add the concept of radv shader binaries.
This simplifies a bunch of stuff by
(1) Keeping all the things in a single allocation, making things easier
 for the cache.
(2) creating a shader_variant creation helper.

This is immediately put to use by creating rtld shader binaries. This
is the main reason for the binaries, as we need to do the linking at
upload time, i.e. post caching. We do not enable rtld yet.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
43f2f01cc8 radv: Add export_prim_id to the shader variant info.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
15046ef7c8 radv: use last nir shader to determine stage in postprocessing
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
7469516244 radv: Merge rsrc1/rsrc2 fields with the config fields.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Andres Gomez
4000428ada vulkan: Update headers to 1.1.113
Some headers were not dragged in the last update(s).

Fixes: 465ec0b145 ("vulkan: Update the XML and headers to 1.1.113")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-07-04 10:37:52 +00:00
Samuel Pitoiset
cce2645810 radv: do not crash when generating binning state for unknown chips
These values are only useful if binning is disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-04 12:22:46 +02:00
Samuel Pitoiset
8a425e057d radv: fix potential crash in the compute resolve path
If the destination attachment is UNUSED.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-04 12:22:43 +02:00
Tomeu Vizoso
0cc02c9ea6 panfrost: Take into account off-screen FBOs
In that case, ctx->pipe_framebuffer.cbufs[0] can be NULL.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Boris Brezillon <boris.brezillon@collabora.com>
Fixes: 5375d009be ("panfrost: Pass referenced BOs to the SUBMIT ioctls")
2019-07-04 10:48:09 +02:00
Christian Gmeiner
f39a7fd627 util/macros: rework DIV_ROUND_UP macro
Simplify used math.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-07-04 10:21:32 +02:00
Christian Gmeiner
e519d3c239 gitlab-ci: bump required libdrm version
Fixes following build problem:
 Message: libdrm 2.4.99 needed because amdgpu has the highest requirement
 Dependency libdrm_intel found: NO found '2.4.97' but need: '>=2.4.99'
 Dependency libdrm_intel found: NO

 meson.build:1178:4: ERROR:  Invalid version of dependency, need 'libdrm_intel' ['>=2.4.99'] found '2.4.97'.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-07-04 09:55:10 +02:00
Kenneth Graunke
9ea67f0a79 iris: Fix MOCS for grid surface
Hardcoding 4 is bad; we have a function for this now.
2019-07-03 22:24:50 -07:00
Kenneth Graunke
10560f8506 iris: Minor tidying 2019-07-03 22:24:44 -07:00
Marek Olšák
6ab23805c3 Revert "mesa/st: Passthrough scissor when clearing by quad"
This reverts commit 0a88aa3025.

It breaks a lot of piglit tests.
2019-07-04 01:08:02 -04:00
Marek Olšák
8dfdf5aae4 gallium/u_blitter: add return to fix the build 2019-07-03 23:44:14 -04:00
Alyssa Rosenzweig
0a88aa3025 mesa/st: Passthrough scissor when clearing by quad
The scissor state -is- setup, but the scissor test is not enabled. This
can prevent certain optimizations from occurring on tilers where
unaffected tiles are thrown out entirely.

v2: Only enable scissor test if the scissor test is actually set by the
app, to avoid regressing quad-based clears used for other reasons (like
a color mask).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-03 14:33:46 -07:00
Nicolai Hähnle
8845a23698 amd: add NAVI10 PCI IDs
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00