lock the entire scope when storing image reqs cache entry to prevent
entry being added between the split locks.
Fixes: b51ff22fbe ("venus: support caching image memory requirements")
Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27401>
the lowering for is_sparse_texels_resident must run after all the instances of
sparse_residency_code_and have been eliminated in order to effectively guarantee
that there are no remaining cases of tex.e (sparse) component access
fixes#10548
Fixes: f0ca477b500 ("zink: run sparse lowering after all optimization passes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27474>
Other drivers such as virgl are planned to be added to d3d10... target.
As it is not a purely software driver d3d10sw target is renamed to
d3d10umd target to reflect that.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27416>
For graphics drivers on windows it is beneficial to have usermode DLLs
names matching driver overall name, example being vm3dum_10.dll and
nvwgf2um.dll for d3d10 usermode drivers from VMWare and Nvidia.
To implement that new meson option `gallium-d3d10-dll-name` that
names the resulting d3d10umd target DLL is introduced. Additionaly,
to avoid confusion `gallium-dll-name` is renamed to `gallium-wgl-dll-name`
as it corresponds to the name used in wgl target.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27416>
When URB state for DS changes, we need to emit URB setup for VS with
256 handles and 0 for rest, commit this using a HDC flush before
setting real values.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
When URB state for DS changes, we need to emit URB setup for VS with
256 handles and 0 for rest, commit this using a HDC flush before
setting real values.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
Patch changes blorp_emit_urb_config to use intel_urb_config so that we
can use it later to communicate blorp urb configuration for drivers.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
Patch adds a structure holding urb configuration. This makes it nicer
to pass it around as example for blorp. We need to be able to sometimes
compare with last urb configuration to be able to implement some
workaround.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
If dual blending is enabled, only 1 output is supported. Multiple
outputs confuse the write combining pass in this case, leading to
incorrect output and/or an assert failure in emit_fragment_store.
The fix is straightforward, just skip the speculative emitting of
multiple outputs in the case where dual source blending is enabled.
This also adds an extra sanity check in `pan_nir_lower_zs_store` to
check for only one blend store being present.
Fixes: c65a9be421 ("panfrost: Preprocess shaders at CSO create time")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9487
Co-Authored-By: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26474>
The introduction of block::reconvergence_point happened at the same time
as scan_clusters.macro so we forgot to set it correctly.
Fixes: 60413e11c2 ("ir3: optimize subgroup operations using brcst.active")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27463>
Besides switching to "ctx.active_mask" as the condition, this is basically
the same.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23367>
On windows when external resources are imported
there is no information about them. And in such cases
resource_from_hanlde templ argument is equal NULL.
To support such case on virgl, virgl winsys can now
fill in template for resource, that will be used if
templ=NULL. Additionally helper functions were
added to convert virgl encoded enums to pipe.
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27308>
While OpenGL requires that VE must be bound,
other mesa frontends, f.e. d3d10umd, can emit draw
without any VE bound. Which led to vctx->vertex_elements
to be null, which lead to null derefence. Add check
for ve not being null to avoid that.
Supported by virglrenderer@b8ac10db
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27308>
* Cast to uint8_t* before doing pointer arithmetics
* Add zero to initializer list to initialize zeroed structs
* Don't include linux sepcific headers on WIN32
* Don't use build_id when it isn't available
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27308>
The kernel checks for UVD msgs and if there aren't any gets upset,
so don't submit 0 length on UVD rings either to avoid that.
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27186>
The CTS image allocation sometimes doesn't try to allocate a complete
DPB, but the amdgpu kernel module checks for this, so always make
the DPB max sized on uvd instances.
Fixes part of video decode on Fiji/Polaris
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27186>
The submit_sub_index field is used by RGP to determine the number of
submits. Previously, it was incorrectly reporting the same number of
submits than command buffers.
Fixes: 88cbe32048 ("radv: add support for RGP queue events")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27439>
r600 can't handle indirect access to kcache 14 and 15, so
if the shader has more than 14 UBOs and there is indirect UBO
access load the values from kcache 14 (and 15) directly and do
a bcsel based on the buffer id to return the right value.
v2: - replace superfluous check with an assert (Triang3l)
- change the lowering pass to work on load_ubo
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10112
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27372>
This only dumps the begin tokens. Tokens are written to a buffer
containing a 12 byte header at the beginning.
We use an intermediate format for the ray history tokens because the RRA
format is very inefficient.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25548>
DRM modifiers are a BSD/Linux phenomenon.
We can also remove a bunch of these checks too. No Linux specific
symbol or header is **actually** used, and the DRM modifier is
just represented as uint64_t. But kept the style of the file
as is.
Reviewed-by: Serdar Kocdemir <kocdemir@google.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27425>
The braces resulted in the never demoting the heap type
which resulted in an infinite loop if this become a necessity.
Fixes: eb394f5316
zink: redesign the allocation try loop to test all heaps
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27446>
