Commit graph

55 commits

Author SHA1 Message Date
Gert Wollny
b9fea5ea6b virgl: Use better reporting for mirror_clamp features
Fixes: 9efe50c83b
    virgl: report MIRROR_CLAMP features better

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27106>
2024-01-29 09:01:26 +00:00
Corentin Noël
b8e06fa48a virgl: Only send the same amount of data than declared in pipe_sampler_state
Adjust the masks to only send the data that we are sure to actually use.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26856>
2024-01-04 11:00:12 +00:00
Andrew Gazizov
d1009481c8 venus: Add use_guest_vram capset to enable guest-based blob alloc
For hypervisors that do not support host memory injection into the
guest address space, it's necessary to have guest-based blob alloc.
Therefore, use a new 'use_guest_vram' virgl capset to decide on
performing guest blob allocations from dedicated heap (Host visible
memory).

Signed-off-by: Andrew D. Gazizov <andrew.gazizov@opensynergy.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25889>
2023-11-06 18:33:15 +00:00
Rob Clark
b90244776a virtio/drm: Split out common virtgpu drm structs
Since these all ended up the same with (not yet merged) intel and amd
implementation of drm native context, split these out so they can be
shared.  This will also make it easier to extract out a shared helper
that can be re-used across native-context drivers.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> # virtio-intel
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24733>
2023-11-04 03:00:04 +00:00
Max R
75f7910850 virgl: Implement clear_render_target and clear_depth_stencil
This functions are required by d3d10umd frontend.
To implement both clear_render_target and clear_depth_stencil
common virgl command VIRGL_CCMD_CLEAR_SURFACE is introduced.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25947>
2023-11-01 20:33:01 +00:00
Gert Wollny
4cdd094ae1 virgl: Use host reported limits for max outputs
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24136>
2023-10-31 13:03:29 +00:00
Gert Wollny
9efe50c83b virgl: report MIRROR_CLAMP features better
The new host version checks the support of these features better,
so report here accordingly. This fixes a number of texwrap piglit
tests on Intel.

v2: Stick to old test for PIPE_CAP_TEXTURE_MIRROR_CLAMP because
    host has to be backward compatible.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25343>
2023-09-25 22:51:20 +00:00
Corentin Noël
c891c1fdce virgl: Cover all the formats defined in the virgl definition
Add all the formats currently defined in u_formats.h

Also make sure that no format on virgl protocol has the same number as another one.
Make so that the virgl_formats_conv_table is following the same order as virgl_formats

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25295>
2023-09-22 07:35:57 +00:00
Feng Jiang
ea5054a94a virgl/video: Add definition of virgl_av1_picture_desc
The virgl_av1_picture_desc references to pipe_av1_picture_desc.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23386>
2023-08-09 09:04:58 +00:00
Boyuan Zhang
7eff5cdbac virgl: Add vp9 picture desc
Define vp9 picture and slice parameters.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
2023-07-19 07:06:38 +00:00
Honglei Huang
9cbb7cb13b virgl/video: Add more pipe type in virgl formats convert table
Add Y8_400_UNORM, YUYV, Y8_U8_V8_444_UNORM,
R8G8_R8B8_UNORM into virgl_formats_conv_table to fix
the resource create fail issue.

Signed-off-by: Honglei Huang <honglei1.huang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
2023-07-19 07:06:38 +00:00
Honglei Huang
e1b8e4d7fc virgl/video: Add support for jpeg decoding
Implement for virgl jpeg decoding.

Signed-off-by: Honglei Huang <honghuan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
2023-07-19 07:06:38 +00:00
Honglei Huang
dad4b79ee0 virgl/video: Add support for vc1 decoding
Implement for virgl vc1 decoding.

Signed-off-by: Honglei Huang <honglei1.huang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
2023-07-19 07:06:37 +00:00
Honglei Huang
deafeab1ee virgl/video: Add support for mpeg12 decoding
Implement for mpeg12 virgl video decoding.

Signed-off-by: Honglei Huang <honglei1.huang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
2023-07-19 07:06:37 +00:00
Gert Wollny
2428fce2e6 virgl: signal support for group vote and draw parameters
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23196>
2023-05-26 13:25:18 +00:00
Gert Wollny
cbb144c8d4 virgl: Add support for ARB_pipeline_statistics
v2: make sure the PIPE enums map corretly to the VIRGL enums (Tintou)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23121>
2023-05-23 14:01:43 +00:00
Gert Wollny
831e7818aa virgl: Enable AMD_vertex_shader_(layer|viewport_index) when host supports it
This increase the number of cases when the texture upload from buffer
can use the PBO upload code path.

v2: Fix logic combination (Corentin)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Ryan Neph
fea4af6234 venus: add supports_multiple_timelines capset and enable
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19691>
2022-12-16 21:12:38 +00:00
Feng Jiang
ebf6158bd0 virgl/video: Add support for H.265 encoding
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Weishi Li <liweishi@kylinos.cn>
Signed-off-by: Liming Sun <sunliming@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
2022-11-18 07:46:11 +00:00
Feng Jiang
d3a203c969 virgl/video: Add support for H.264 encoding
Implement encoding framework and support H.264 encoding.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Ming Xie <xieming@kylinos.cn>
Signed-off-by: Liming Sun <sunliming@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
2022-11-18 07:46:11 +00:00
Boyuan Zhang
69ed5f13d8 virgl/video: Pass "max_references" to backend when creating a video codec
The "max_references" is an important value in sequence parameters,
which will be used when encoding SPS headers.

Signed-off-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
2022-11-18 07:46:11 +00:00
Feng Jiang
316652a4bb virgl/video: Move hardware-related definitions from virgl_video.h to virgl_video_hw.h
Considering the increasing number of hardware-related definitions,
it is better to put them in a separate file.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
2022-11-18 07:46:11 +00:00
Corentin Noël
086b620793 virgl: Add TEXTURE_SHADOW_LOD capability support
Bind PIPE_CAP_TEXTURE_SHADOW_LOD with its value so that we are not using
non-existing GLSL on host side.

Rename VIRGL_CAP_FAKE_FP64 into VIRGL_CAP_HOST_IS_GLES

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18296>
2022-09-29 15:06:29 +00:00
Gert Wollny
95cea62a9b virgl: Report CONSTANT_BUFFER_SIZE according to GL_MAX_UNIFORM_BLOCK_SIZE
GL_MAX_FRAGMENT_UNIFORM_COMPONENTS may not report a size that
is useful to calculate the supported UBO size. Use the value
GL_MAX_UNIFORM_BLOCK_SIZE instead when the host supports this.

Related: https://gitlab.freedesktop.org/virgl/virglrenderer/-/issues/286
Fixes: 5b683ba19a
  virgl: Only progagate the uniform numbers if the numbers are actually right

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18512>
2022-09-10 15:23:57 +00:00
Gert Wollny
1d8627deed virgl: Add some formats that the CTS uses
Otherwise running the CTS emits lots of warnings about
these formats missing in the drivers format table.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18462>
2022-09-08 06:38:48 +00:00
Gert Wollny
be012932d0 virgl: Fix ubsan warnings:
virgl_screen.c:313:55: runtime error: left shift of 1 by 31 places cannot be represented in type 'int'
virgl_screen.c:682:27: runtime error: left shift of 1 by 31 places cannot be represented in type 'int'
virgl_encode.c:481:7: runtime error: left shift of 1 by 31 places cannot be represented in type 'int'

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18231>
2022-08-29 05:44:22 +00:00
Feng Jiang
6b5aecb195 virgl: add support for hardware video acceleration
Currently H.264 and H.265 decoding is supported, and other profiles
and encodings will be added in the future.

This function relies on the virglrenderer commit:
a92fed821f5ac173ca82c011a5d7e5b25e7bd0eb

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Ming Xie <xieming@kylinos.cn>
Signed-off-by: Liming Sun <sunliming@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17157>
2022-08-11 10:21:03 +00:00
Dave Airlie
a26543f636 virgl: abstract virgl shader stages from pipe shader stages.
If the gallium ones get reordered, add the abstraction to the virgl
wire types.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17747>
2022-08-04 08:17:39 +00:00
Gert Wollny
bf29ebc0a7 virgl: Submit the TGSI_PROPERTY_SEPARABLE_PROGRAM when the host understands it
We can't unconditionally support separable shader objects on the host,
so submit the property only if the shader is actually separable, the
host knows about the property, and supports SSO.

Without support for SSOs, the  host can still compile and link the shaders,
it needs to do more  work on interface matching though.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17344>
2022-07-07 09:46:53 +00:00
Corentin Noël
d92c1ca01b virgl: Add support for passing the supported number of components from virgl
Return the capabilities reported by the host. No functional change in case the
host virgl implementation doesn't implement it.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16401>
2022-07-06 13:12:38 +00:00
Yiwei Zhang
9f9d543b12 venus: renderer to store allow_vk_wait_syncs capset
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16731>
2022-06-16 19:00:36 +00:00
Rob Clark
cb5f25ea71 freedreno/drm/virtio: Protocol updates
This syncs up with the protocol of what eventually landed in virglrender.

1) Move all static params to capset to avoid having to query host
   (reduce synchronous round trips at startup)
2) Use res_id instead of host_handle.. costs extra hashtable lookups in
   host during submit, but this lets us (with userspace allocated IOVA)
   make bo alloc and import completely async.
3) Require userspace allocated IOVA to simplify the protocol and not
   have to deal with GEM_NEW/GEM_INFO potentially being synchronous.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16086>
2022-04-27 23:10:00 +00:00
Rob Clark
e6b2785811 freedreno/drm/virtio: Use userspace IOVA allocation
If supported by host virglrenderer and host kernel, use userspace
allocated GPU virtual addresses.  This lets us avoid stalling on
waiting for response from host kernel until we need to know the
host handle (which is usually not until submit time).

Handling the async response from host to get host_handle is done
thru the submit_queue, so that in the submit path (hot) we do not
need any additional synchronization to know that the host_handle
is valid.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16086>
2022-04-27 23:10:00 +00:00
Yiwei Zhang
2223f13b26 venus: store extension mask in renderer info
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15495>
2022-04-09 00:19:05 +00:00
Rob Clark
802f4da5ee freedreno/drm: Add virtio backend
Add a new backend to enable using native driver in a VM guest, via a new
virtgpu context type which (indirectly) makes host kernel interface
available in guest and handles the details of mapping buffers to guest,
etc.

Note that fence-fd's are currently a bit awkward, in that they get
signaled by the guest kernel driver (drm/virtio) once virglrenderer in
the host has processed the execbuf, not when host kernel has signaled
the submit fence.  For passing buffers to the host (virtio-wl) the egl
context in virglrenderer is used to create a fence on the host side.
But use of out-fence-fd's in guest could have slightly unexpected
results.  For this reason we limit all submitqueues to default priority
(so they cannot be preepmted by host egl context).  AFAICT virgl and
venus have a similar problem, which will eventually be solveable once we
have RESOURCE_CREATE_SYNC.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14900>
2022-03-25 02:03:30 +00:00
Corentin Noël
2aa8e56e52 virgl: Update virgl_protocol and use the provided constants
Allow for better readability of the code.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14473>
2022-03-24 10:50:21 +01:00
Akihiko Odaki
b70f14188d virgl: Check texture multisample compatibility
v2: Support VIRGL_FORMAT_NONE (Gert Wollny)

Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Suggested-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15115>
2022-03-10 10:34:12 +00:00
Gert Wollny
c9d99b7eec virgl: Fix texture transfers by using a staging resource
This commit fixes the following flaws in the implementation:

* when a resource was re-allocated, the guest side storage
  was also allocated
* when a source needs a readback before being written to, then
  the call would go through vws->transfer_get, thereby bypassing the
  staging resource, and this would fail on the host, because no
  the allocated IOV was too small (just one byte)
* if the texture write would need neither flush nor readback, the
  old code path would be used expecting that guest side backing stogage
  for the texture.

v2: - actually do a readback to the stageing resource when it is required
    - fix typo (Lepton)

v3: Don't use stageing transfers if the host can't read back the data
    by rendering to an FBO or calling getTexImage, because in this case
    we rely on the IOV to hold the date.

v4: Also don't use staging transfers if the format is no readback
    format. Otherwise we have to deal with the resolve blit, and
    this is currently not working correctly.

v5: add a new flag that indicates whether non-renderable textures can
    be read back (either via glGetTexImage or GBM)

v6: Restrict the use of staging texture transfers to textures that can
    be read back, and on GLES also if the they are bound to scanout and
    the host uses minigbm to allocate such textures.
    For that replace the flag indicating the capability to read back
    non-renderable textures with a cap that indicates whether scanout
    textures can be read back.

v7: update virglrenderer version in the CI

v8: update use of stageing (Chia-I)

v9: remove superflous check and assignment (Chia-I)

v10: disable stageing textures for arrays with stencil format. This is a
     workaround for failures of the CI.

Fixes: cdc480585c
    virgl/drm: New optimization for uploading textures

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14495>
2022-03-08 23:39:27 +01:00
Chia-I Wu
b14dd3a866 venus: prefer VIRTGPU_BLOB_MEM_HOST3D for shmems
They are logically contiguously in the host.  More importantly, they
enable host process isolation.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13800>
2021-12-08 21:23:05 +00:00
mwezdeck
cdc480585c virgl/drm: New optimization for uploading textures
1. We can create resource with size of "1" on drm, because size
   is not passed to the renderer.
2. We can't create resource with size of "1" on vtest, because shmem
   is created based on that.
3. If renderer supports copy_transfer_from_host, then use staging
   buffer for transfer in both ways to and from host.

This will allow to reduce memory consumption in the guest.

v2:
   - add inline function for checking if we can use this optimization
   - add check in readback path. If renderer doesn't support
     copy transfer from host, then we need to go with previous
     path in readback (through transfer_get ioctl)

v3:
   - fix logic for readback

v4:
   - refactor the implementation to integrate it more to
     existing code base

v5:
   - reuse COPY_TRANSFER3D in both directions

v6:
   - encode direction in COPY_TRANSFER3D if host supports it

v7:
   - renamed cap bit
   - introduced COPY_TRANSFER3D_SIZE_LEGACY define

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13689>
2021-12-08 14:01:48 +00:00
Antonio Caggiano
902c5bf468 virgl: Link shader program
Add a new command associated to glLinkProgram. With this we should be
able to compile and link shaders when requested by the user, thus
avoiding that to happen in the middle of a frame.

Together with the command we pass an array of shader handles attached to
the program, where each position of the array corresponds to a pipe
shader type.

Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13674>
2021-11-23 16:14:16 +00:00
Gert Wollny
63c4c559cb virgl: obtain supported number of shader sampler views from host
Modern games may use more than 16 sampler views, so get what the host
actually supports, and default to 16 on old hosts that don't pass the
value.

Since the possible maximal value of PIPE_MAX_SHADER_SAMPLER_VIEWS doesn't
fit into an uint32_t remove the binding flags, they were only used for
releasing the sampler views, and this can be achieved differently.

v2: Fix compilation error

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: John Bates <jbates@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13646>
2021-11-08 19:34:30 +00:00
Dave Airlie
2116a4f5cc virgl: add support for anisotropic texture filtering
This is the guest side for adding correct anisotropic filtering support

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11944>
2021-08-04 10:49:55 +00:00
Yiwei Zhang
d0d1b66d8e virgl: forward the host renderer hardware info
Some game engines rely on the real hardware info to adjust default
graphics quality and other attributes.

Prepend "virgl" to avoid app compat issues and to distinguish from
native platforms while giving engines/apps a chance to adjust graphics
defaults.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11179>
2021-06-11 06:47:02 +00:00
Italo Nicola
32f710c09d virgl: implement EXT_multisampled_render_to_texture
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10500>
2021-05-18 18:54:16 +00:00
Lepton Wu
5322572c78 virgl: move new added field to the end.
This field was introduced 2 months ago and it breaks virgl
compatibility between guest/host. Switch the new added field
to the end. We will still have compatibility issue but the
"bug window" is much smaller.

Fixes: e778aceaae ("virgl: update headers")

Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10333>
2021-04-20 00:00:30 +00:00
Chia-I Wu
dab339b07e virgl: update headers from virglrenderer
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5800>
2021-04-08 17:15:37 +00:00
Gert Wollny
8bc9ae1bc6 virgl: implement support for PIPE_CAP_STRING_MARKER
With this command implemented messages emitted by
applications via glDebugMessageInsert will be forwarded
to the host.

v2: - remove check for feature in encode function, this
      is covered in the state tracker (Rohan)
    - reorder parameters in the encode function to the
      order of the emit callback

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9433>
2021-03-09 13:57:05 +00:00
Rohan Garg
c6eb84ff30 virgl: Add support for querying detailed memory info
This allows for virgl guests to expose GL_NVX_gpu_memory_info and
GL_ATI_meminfo when the extensions are supported on the host.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9337>
2021-03-04 17:14:14 +01:00
cheyang
6f4c4df6c2 virgl: add astc 2d compressed formats
Signed-off-by: cheyang <cheyang@bytedance.com>
Signed-off-by: hexin   <hexin.op@bytedance.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9306>
2021-03-04 09:03:47 +00:00