Commit graph

1761 commits

Author SHA1 Message Date
Keith Packard
67a2c1493c vulkan: Add VK_EXT_calibrated_timestamps extension (radv and anv) [v5]
Offers three clocks, device, clock monotonic and clock monotonic
raw. Could use some kernel support to reduce the deviation between
clock values.

v2:
	Ensure deviation is at least as big as the GPU time interval.

v3:
	Set device->lost when returning DEVICE_LOST.
	Use MAX2 and DIV_ROUND_UP instead of open coding these.
	Delete spurious TIMESTAMP in radv version.

	Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
	Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

v4:
	Add anv_gem_reg_read to anv_gem_stubs.c

	Suggested-by: Jason Ekstrand <jason@jlekstrand.net>

v5:
	Adjust maxDeviation computation to max(sampled_clock_period) +
	sample_interval.

	Suggested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
	Suggested-by: Jason Ekstrand <jason@jlekstrand.net>

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-17 20:10:15 -07:00
Marek Olšák
fedc1fda30 radeonsi: save raster config in screen, add se_tile_repeat 2018-10-16 15:28:22 -04:00
Samuel Pitoiset
647c2b90e9 radv: disable VK_SUBGROUP_FEATURE_VOTE_BIT
This feature isn't used for now, so disable it until
wwm is fixed in LLVM.

Fixes dEQP-VK.subgroups.vote.graphics.subgroupallequal*

https://bugs.freedesktop.org/show_bug.cgi?id=108115
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-16 10:24:19 +02:00
Samuel Pitoiset
593996bc02 radv: implement buffer to image operations for R32G32B32
This should fix rendering issues with Batman Arkham City.
We will probably need to implement itob and itoi at some
point, but currently nothing hits these paths.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107765
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-16 09:22:38 +02:00
Samuel Pitoiset
26a2ce35ab radv: do not force the flat qualifier for clip/cull distances
This fixes some new CTS that reads clip/cull distances
from the fragment shader stage:

dEQP-VK.clipping.user_defined.clip_*

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-15 21:55:28 +02:00
Samuel Pitoiset
80c84bdba9 radv: bump discreteQueuePriorities to 2
It's the minimum value required by the spec.

This fixes dEQP-VK.api.info.device.properties.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-15 21:55:25 +02:00
Bas Nieuwenhuizen
6ed0fd24d4 radv: Implement VK_EXT_pci_bus_info.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-15 12:27:49 +02:00
Samuel Pitoiset
2c139e2cdf radv: do not support blitting surfaces for R32G32B32 formats
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-12 15:28:21 +02:00
Samuel Pitoiset
229803b66a radv: implement clear operations for R32G32B32
This fixes crashes for some CTS:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.linear_*_*
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.*_linear_*

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-11 14:49:16 +02:00
Samuel Pitoiset
c3ba3c2611 radv: disallow 3D images and mipmaps/layers for R32G32B32 linear formats
R32G32B32 are weird formats and we are only going to support
some basic operations for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-11 14:49:14 +02:00
Samuel Pitoiset
d179312b53 radv: add a workaround for a VGT hang with prim restart and strips
Otherwise, Yakuza and The Evil Within hang the GPU with DXVK.
This apparently only works on Polaris.

Suggested by Marek.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-11 10:16:11 +02:00
Dave Airlie
600d8ecb57 radv: remove unsigned comparison against 0
The value is always >= 0 here.

Found by coverity

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-11 10:19:20 +10:00
Dave Airlie
6e1d294804 radv: remove dead code for master_fd close
We have never opened master_Fd at this point, so remove code to
close it.

Found by coverity.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-11 10:19:16 +10:00
Dave Airlie
7c04b96f03 radv: don't pass shader key by copy
Coverity pointed out we were copying 168 bytes here unnecessarily.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-11 10:18:43 +10:00
Eric Engestrom
976188737d radv: add missing meson c++ visibility arguments
Fixes: 6f3aee40f9 "radv: using tls to store llvm related info
                             and speed up compiles (v10)"
Cc: Dave Airlie <airlied@redhat.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-10-09 14:22:24 +01:00
Samuel Pitoiset
d3682766f6 radv: tidy up radv_pipeline_init_multisample_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08 14:17:43 +02:00
Samuel Pitoiset
b38228ccb0 radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK
It has probably no effect without out of order rasterization
anyway.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08 14:17:40 +02:00
Samuel Pitoiset
937986ca1d radv: set DB_EQAA.INCOHERENT_EQAA_READS
My attempt was to set this field instead of duplicating one.

Fixes: 6cfa321c39 ("radv: add potential missing fields for DB_EQAA")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08 14:17:33 +02:00
Marek Olšák
fa023f293e ac: correct PKT3_COPY_DATA definitions 2018-10-06 21:50:09 -04:00
Marek Olšák
a668c8d6ba ac: define all address spaces properly 2018-10-06 21:50:09 -04:00
Samuel Pitoiset
2b34985d93 radv: fix resetting the pool for timestamp queries
Since the driver no longer uses the availability bit for
timestamp queries it shouldn't reset it. Instead, it should
reset the query values to UINT32_MAX. This fixes VM faults.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108164
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-10-04 10:56:25 +02:00
Timothy Arceri
ea66bfda88 util: disable cache if we have no build-id and timestamp is zero
Timestamp can be zero for example when Flatpak is used. In this
case just disable the cache rather then segfaulting when
incompatible cache items are loaded.

V2: actually return false when mtime is 0.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-02 22:07:55 +10:00
Samuel Pitoiset
c2867e4c2a radv: do not try to set DCC_CONTROL when image doesn't use DCC
Unnecessary. While we are at it, remove the check for pre-VI
because it's already checked earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 12:13:12 +02:00
Samuel Pitoiset
f622ab889a radv: add a sanity check for mutable formats and TC-compat HTILE
If apps use the MUTABLE bit and the same formats as the image one
in the list, we can still enable TC-compat HTILE. I don't think
this happens often but given the fact that TC-compat HTILE allows
a nice boost in some situations, it's worth checking.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 12:13:09 +02:00
Samuel Pitoiset
dc91c4d40a radv: disable HTILE for very small depth surfaces
Like we disable DCC/CMASK for small color surfaces as well.
Serious Sam 2017 creates a 1x1 depth surface and I think
it should be faster to do slow clears on the graphics queue
instead of fast clears on compute, and eventually a depth
expand if the surface isn't TC-compatible HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 10:16:33 +02:00
Samuel Pitoiset
6cfa321c39 radv: add potential missing fields for DB_EQAA
Other drivers set these two as well, just apply the same rule.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 10:16:30 +02:00
Samuel Pitoiset
bd6df2f923 radv: disable complicated point clipping against user clip planes
I don't think this is required by Vulkan too.

Ported from RadeonSI (AMDVLK doesn't set it either).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 10:16:25 +02:00
Samuel Pitoiset
3fb4adae83 radv: do not sync CP DMA when copying buffers
We already track if the DMA engine is busy/idle with a flag,
and we emit a packet that waits for all CP DMA operations
to be complete. This is done at end of command buffer because
the kernel doesn't wait for them, and also when emitting
barriers, so it should be safe.

This improves small copies for both aligned and unaligned sizes.

Aligned sizes:
BEFORE:
1 KB: 59.840000 ms
2 KB: 71.200000 ms
AFTER:
1 KB: 31.200000 ms
2 KB: 31.040000 ms

Unaligned sizes:
BEFORE:
2 KB: 68.3200 ms
3 KB: 79.3600 ms
5 KB: 76.6400 ms
9 KB: 90.8800 ms
17 KB: 116.0000 ms
AFTER:
2 KB: 31.0400 ms
3 KB: 32.0000 ms
5 KB: 30.8800 ms
9 KB: 30.5600 ms
17 KB: 29.6000 ms

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-28 09:08:52 +02:00
Samuel Pitoiset
621e70dd40 radv: adjust the CmdUpdateBuffer threshold for optimal performance
According to my benchmark results, it appears that we should
reduce the threshold to 1024.

BEFORE:
1 KB: 68.656000 ms
2 KB: 118.368000 ms

AFTER:
1 KB: 31.760000 ms
2 KB: 29.840000 ms

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-28 09:08:44 +02:00
Samuel Pitoiset
5d6a560a29 radv: do not use the availability bit for timestamp queries
It's unnecessary because we can just check if the timestamp
is to different to the default value when a pool is created
or resetted. Instead of waiting for the availability bit to
be 1, we have to emit a not equal WAIT_REG_MEM for checking
if the timestamp is ready.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-09-28 09:08:03 +02:00
Bas Nieuwenhuizen
40585ddb48 radv: Remove garbage comment.
Trivial.
2018-09-27 02:04:06 +02:00
Bas Nieuwenhuizen
0207ebcbf1 radv: Do not use multiple draws for multisample copies.
Use sample rate shading instead, should give better locality.

Makes Nier with 8x msaa on a Raven go 5 fps -> 7 fps in the menu.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-09-27 02:04:00 +02:00
Andres Rodriguez
ec1fcf92ae radv: only emit ZPASS_DONE for timestamp queries on gfx queues
A ZPASS_DONE packet doesn't make sense for the compute queue. It will
result in a gpu hang.

This change resolves a gpu hang for SteamVR+Vega.

Cc: mesa-stable@lists.freedesktop.org
Fixes: 1f616a840e "radv: emit a dummy ..."
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-09-25 02:30:34 -04:00
Timothy Arceri
72e4287e8f radv: make use of nir_lower_load_const_to_scalar()
This allows NIR to CSE more operations. LLVM does this also so the
impact is limited, however doing this in NIR allows other opts to
make progress. For example in radeonsi more loops are unrolled in
Civilization Beyond Earth.

The actual pipeline-db stats are not overwhelming but even in the
negatively affected shaders the NIR is clearly better. It just
happens that the code shuffling and in some cases calls to max
rather than a flt result in the final output from LLVM not
giving as good numbers.

However this is an incremental opt that further passes build off
so the change should be made IMO.

Totals from affected shaders:
SGPRS: 20192 -> 20184 (-0.04 %)
VGPRS: 19516 -> 19524 (0.04 %)
Spilled SGPRs: 437 -> 444 (1.60 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1527444 -> 1522276 (-0.34 %) bytes
LDS: 6 -> 6 (0.00 %) blocks
Max Waves: 1018 -> 1016 (-0.20 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-25 09:31:22 +10:00
Samuel Pitoiset
fe3f13cc5a radv: use the resolve compute path if dest uses multiple layers
The hardware path doesn't support resolving layers, for both
source and destination images.

This fixes a reflection issue when MSAA is enabled which
affects GTA V and probably DIRT3.

CC: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107786
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Gregor Münch <gr.muench_at_gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-21 16:35:59 +02:00
Jason Ekstrand
ab80889e92 anv,radv: Implement vkAcquireNextImage2
This was added as part of 1.1 but it's very hard to track exactly what
extension added it.  In any case, we should implement it.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Dave Airlie <Airlied@redhat.com>
2018-09-21 07:02:35 -05:00
Samuel Pitoiset
674fcfaecc radv: only enable shaderInt16 on GFX9+ and LLVM7+
The throughput is similar to 32-bit integers on GFX8 and
AMDVLK does not expose 16-bit integers on pre Vega as well.
On GFX9+, only LLVM 7+ has support.

This fixes a bunch of CTS crashes on GFX9/LLVM 6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-21 10:56:17 +02:00
Bas Nieuwenhuizen
0a77e70d10 radv: Fix driver UUID SHA1 init.
Was missing the init, found by Emil.

Fixes: d17443a459 "radv: Use build ID if available for cache UUID."
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-09-20 23:38:38 +02:00
Samuel Pitoiset
121f226471 radv: use a 64-bit unsigned integer when allocating a descriptor pool
pool->size is a 64-bit unsigned integer too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-19 13:36:12 +02:00
Samuel Pitoiset
35656823b9 radv: enable VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
All CTS pass on Polaris/Vega with LLVM 6, 7 and master, so
I think it's safe to enable the feature.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-19 13:36:10 +02:00
Samuel Pitoiset
febdc13a6c radv: do not support blitting surfaces with depth and stencil
Fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint.optimal_optimal_nearest

And all friends that try to blit a surface with different
depth and stencil formats.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-19 13:36:07 +02:00
Bas Nieuwenhuizen
95bb7d82ca Revert "radv: fix descriptor pool allocation size"
This reverts commit 90819abb56.

This logic was wrong, the original code is correct. The direct
impact is that we allocate up to approximately a squared amount
of memory compared to what we should allocate.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-09-18 22:51:42 +02:00
Samuel Pitoiset
c9dbe52f84 radv: implement VK_EXT_conservative_rasterization
Only supported by GFX9+.

The conservativeraster Sascha demo seems to work as expected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-18 13:28:01 +02:00
Samuel Pitoiset
450a325858 radv: do not re-create the sampler for every blits in CmdBlitImage()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-18 13:27:59 +02:00
Samuel Pitoiset
3871dd7a92 radv: allow to force anisotropy via RADV_TEX_ANISO
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-18 13:27:58 +02:00
Bas Nieuwenhuizen
d17443a459 radv: Use build ID if available for cache UUID.
To get an useful UUID for systems that have a non-useful mtime
for the binaries.

I started using SHA1 to ensure we get reasonable mixing in the
various possibilities and the various build id lengths.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-09-17 20:19:52 +02:00
Samuel Pitoiset
08103c5f65 radv: enable shaderInt16 capability
Not sure if this is all wired up. CTS does pass and the Tangrams
demo works fine on Vega. There are corruption issues on Polaris
but not sure if that related to 16-bit support.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-17 15:18:39 +02:00
Samuel Pitoiset
aec9151464 radv: fix use of unreachable() in the meta blit path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-09-17 11:29:25 +02:00
Samuel Pitoiset
6521d4a659 Revert "radv: Optimize rebinding the same descriptor set."
This introduces random GPU hangs on Vega, at least.

This reverts commit 02a43edf18.
2018-09-17 11:20:57 +02:00
Samuel Pitoiset
90819abb56 radv: fix descriptor pool allocation size
The size has to be multiplied by the number of sets.

This gets rid of the OUT_OF_POOL_KHR error and fixes
a crash with the Tangrams demo.

CC: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-17 10:18:01 +02:00