We already have a default case, there is no need to specify each invalid
primitive topology explicitly.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41654>
Geometry shaders are going to need to be able to replace direct draws
with indexed draws and indexed draws with indexed draws with a different
index buffer. In order to facilitate this, stop trusting in the API
level dirty bits and instead plumb it through the draw info and track
the hardware state separately on CSF.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41654>
This unifies the setup code between direct and indirect draws a bit.
There's now one panvk_cmd_draw() helper which calls into the prepare*()
helpers and then calls a direct or indirect launch_*draw() helper. This
new helper takes a copy of the panvk_draw_info, not pointer, because it
may modify it as part of executing the polygon pipeline.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41654>
Once we start actually compiling variants, it's going to be much more
convenient if we only have one descriptor table per logical shader. All
the variants can fetch from the one set of tables. We can't duplicate
push, however, because that depends on the behavior of the back-end
compiler and might be different per-variant.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41654>
There are some important ordering factors here but there's no reason why
these can't be done closer together or why we can't group FS and VS
together. Also, now that we know we check fs != NULL before calling
either desc/SSBO prepare helper, we can drop the shader checks from
them.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41654>
This breaks most of the loop out into a new prepare_draw_layer() helper
which does all the allocations and state management, leaving the caller
to execute the actual jobs.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41654>
Enable the extension and its read-access features, gated to PAN_ARCH >= 9.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42043>
Add panvk_nir_lower_tile_image which turns load_tile_image into
a load_tile_pan. Color reads take their conversion from the input
attachment map at runtime, so the compiled shader stays format-independent
and the on-disk cache is not poisoned across pipelines differing only in
attachment format. Depth and stencil reads use a zero conversion.
The fs variant records which color, depth and stencil tiles are read so
the draw code can fold them into the attachment read masks, and those
flags are serialized into the shader cache.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42043>
Emit load_tile_image for the OpColor/Depth/StencilAttachmentReadEXT
opcodes. The NonCoherent* execution modes select a relaxed, non-coherent
read.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42043>
VK_EXT_shader_tile_image lets a fragment shader read the current pixel's
color, depth or stencil value. The read is per-sample and the attachment
index can be dynamic - neither expressible with load_output - and the
tile read itself is driver-specific. Add a dedicated intrinsic so the
shared SPIR-V front end stays driver-agnostic and each driver lowers it
to its own tile read.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42043>
gallivm can now run no-integers vertex shaders through the NIR path, so
stop converting i915 vertex shaders to TGSI by hand before passing them
to draw.
Also tweak the nir_options so we stop producing the replicating fdots
and flrps (those originate in nir_lower_bool_to_float when
.has_fused_comp_and_csel is false). The constant buffer stride change is
required since with the default stride of 4*sizeof(float) the number of
constant slots corresponds to the number of vec4 constants, but the
gallivm load_ubo out of bound check is not expecting this and would
reject most of the lowered load_ubo_vec4 as out of bound.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41625>
This is only relevant for no_integers drivers that hand NIR to draw, so
anyone doing nir_to_tgsi manually before passing the shader to draw will
still stay on the old path.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41625>
nir_lower_int_to_float rewrites integer ALU to float ALU, but intrinsics
keep their original integer input/output contracts. That can leave UBO
offsets as floatized values feeding integer intrinsic sources, and draw
system value results feeding floatized ALU as raw integer bit patterns.
Add a no_integers intrinsic fixup pass that casts UBO sources back to
integer and draw system value results back to float after
nir_lower_int_to_float.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41625>
the previous hack (reserve flag 0 for ballots) was inflexible and wrong.
instead, track which flags are safe for ballots and insert zeroing operations on
the fly to handle. fixes assertion fail in MHW fosil.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42287>
Daniel says aco does this and I can see the advantage. I am like... 50% certain
this is a reasonable idea.
SIMD16:
Totals from 60 (0.85% of 7050) affected shaders:
Instrs: 523662 -> 519226 (-0.85%); split: -0.88%, +0.03%
CodeSize: 7335104 -> 7268912 (-0.90%); split: -0.94%, +0.04%
Number of fill instructions: 749 -> 565 (-24.57%)
SIMD32:
Totals from 1464 (20.77% of 7050) affected shaders:
Instrs: 7645696 -> 6919642 (-9.50%); split: -9.53%, +0.04%
CodeSize: 109071024 -> 98474160 (-9.72%); split: -9.76%, +0.05%
Number of spill instructions: 44798 -> 42295 (-5.59%); split: -5.62%, +0.03%
Number of fill instructions: 179633 -> 92568 (-48.47%); split: -49.59%, +1.13%
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42287>
This is what aco does, it's simpler and easier to reason about for when we start
adding UGPR issues into the mix. It's probably faster too.
Some stats changes due to dead phis in rare cases (on complex shaders that are
spilling a bunch anyway)... I'm not super worried perso.
SIMD16:
Totals from 12 (0.45% of 2647) affected shaders:
Instrs: 239603 -> 239711 (+0.05%); split: -0.01%, +0.05%
CodeSize: 3430624 -> 3432352 (+0.05%); split: -0.00%, +0.05%
SIMD32:
Totals from 316 (11.94% of 2647) affected shaders:
Instrs: 1407660 -> 1409173 (+0.11%); split: -0.20%, +0.31%
CodeSize: 20224900 -> 20243428 (+0.09%); split: -0.21%, +0.30%
Number of fill instructions: 29298 -> 29937 (+2.18%)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42287>
