Commit graph

204897 commits

Author SHA1 Message Date
Samuel Pitoiset
caf05cba12 ac/surface: select a different swizzle mode for ASTC formats on GFX12
It seems only 4KiB swizzle works fine with ASTC.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34877>
(cherry picked from commit 2af3ef9305)
2025-07-16 16:23:08 +02:00
José Roberto de Souza
b379dca31d anv: Do not emit batch_emit_fast_color_dummy_blit() for video engine
Wa_16018063123 don't apply to video engine also video engine don't
support XY_FAST_COLOR_BLT.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Fixes: ec43c20182 ("anv: implement dummy blit for Wa_16018063123")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
(cherry picked from commit 926e6a94ad)
2025-07-16 16:23:08 +02:00
José Roberto de Souza
a52ae19823 anv: Flush before invalidate aux map in copy and video engines
BSpec: 43904
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 46f5359238 ("anv: Invalidate aux map for copy/video engine")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
(cherry picked from commit 4618a99a4c)
2025-07-16 16:23:08 +02:00
José Roberto de Souza
57c189dbc8 anv: Read the correct register for aux table invalidation when in GPGPU mode in render engine
For 3D or GPGPU modes the same render engine should be used, CCS
register should only be used when using compute engine.

Fixes: 46f5359238 ("anv: Invalidate aux map for copy/video engine")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
(cherry picked from commit e68f81eaf6)
2025-07-16 16:23:08 +02:00
Faith Ekstrand
56d41c6a9e nak: Surface handles are not allowed to be rZ
The chances of this happening are near zero with the way we do surface
ops today but I have seen it in the wild and this is apparently a rule.
The hardware throws an illegal instruction encoding if it sees 255.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35895>
(cherry picked from commit 19bee26056)
2025-07-16 16:23:07 +02:00
Samuel Pitoiset
d1581108b8 ac/surface: use align with NPOT for estimating surface size
ac_estimate_size() triggers an assertion because the block size isn't
aligned to a power of two for ASTC formats.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35879>
(cherry picked from commit cb6f2d9409)
2025-07-16 16:23:07 +02:00
Eric Engestrom
7dd9208c43 freedreno/ci: fix a750-piglit-cl rules
Fixes: 5b3f7de99f ("ci/freedreno: Introduce OpenCL testing for Adreno 618, 660, and 750")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35888>
(cherry picked from commit 32fe81a02b)
2025-07-16 16:23:07 +02:00
Mike Blumenkrantz
76dda44a19 aux/trace: always finish dumping draw/dispatch calls before triggering them
this avoids deadlocks

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35769>
(cherry picked from commit f946167e30)
2025-07-16 16:23:07 +02:00
Samuel Pitoiset
3888ef933a radv: disable RB+ with E5B9G9R9 to workaround failures on GFX10.3-GFX11.5
This looks like a hw bug on GFX10.3-GFX11.5 because RB+ seems to only
work as expected when all channels (RGBA) are written. With that format,
RGB channels must be all set or unset but setting the A channel is
legal so far.

This will reduce rendering performance with that format but it's the
less intrusive solution for now. This might be revisited in the near
future, also with more VKCTS coverage.

This has been tested and verified on GFX10.3 (NAVI21) and GFX11
(NAVI31) and GFX12 (NAVI48), unfortunately I don't have GFX11.5 but
let's assume it's broken there too.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13371
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35631>
(cherry picked from commit 10ef9c6a80)
2025-07-16 16:23:07 +02:00
Samuel Pitoiset
4dac50e381 radv: stop disabling the alpha optimization with E5B9G9R9 and RB+
This old workaround was added due to test failures with VKCTS but it
turns out the tests were broken. Color writemask for E5B9G9R9 must be
all RGB or none and some tests are testing various RGB channels which
is illegal.

See https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/5821.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35631>
(cherry picked from commit 7017b25d6a)
2025-07-16 16:23:07 +02:00
Caio Oliveira
580c4c56e9 brw: Use the right width in brw_nir_apply_key for BS shaders
Fixes: 23c7142cd6 ("anv: disable SIMD16 for RT shaders")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35798>
(cherry picked from commit c733f07378)
2025-07-16 16:23:07 +02:00
Rhys Perry
05364ea153 aco/ra: fix repeated compact_linear_vgprs() in get_reg()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: b7738de4f9 ("aco/ra: rework linear VGPR allocation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13431
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35838>
(cherry picked from commit dce1d4ad4c)
2025-07-16 16:23:07 +02:00
Boris Brezillon
1a3d54dab2 panvk: Lower maxImageDimension{2D,3D,Cube} to match the HW caps
Maximum texture dimension is 2^16, but we're limited by the 32-bit
fields that are used to pass strides/sizes in various descriptors.
Assuming RGBA32_FLOAT is the biggest format we support, that gives us a
16k-1 image size for 2D and cube map, and 512 for 3D.

Change our GetPhysicalDeviceImageFormatProperties2() implementation so
that smaller formats can still advertise bigger image sizes.

Fixes: d5ed77800e ("panvk: Fix GetPhysicalDeviceProperties2() to report accurate info")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35555>
(cherry picked from commit e25a91d919)
2025-07-16 16:23:07 +02:00
Eric Engestrom
2b8877baff meson: only run symbols-check if nm is available
And drop the redundant check from symbols-check.py, which was actually
masking all kinds of issues.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit 4be493862d)
2025-07-16 16:23:07 +02:00
Eric Engestrom
a8b6bbc5a1 bin/symbols-check: document new platform symbols exported since symbols-check was broken
The `pthread_mutexattr_*` symbols probably shouldn't be exported, but
let's fix that later so that we can at least get symbols-check to run
again ASAP.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit f350803fb3)
2025-07-16 16:23:07 +02:00
Eric Engestrom
951751fe1c bin/symbols-check: sort platform symbols
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit f06fff8148)
2025-07-16 16:23:07 +02:00
Eric Engestrom
a0875f4eb0 bin/symbols-check: ignore version of platform symbols
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit 3d9b76db8e)
2025-07-16 16:23:07 +02:00
Eric Engestrom
94bd0d9a23 bin/symbols-check: ignore nm lines that don't have a symbol name
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit 5672230c19)
2025-07-16 16:23:07 +02:00
Eric Engestrom
8d4df0c45d bin/symbols-check: fix fields length condition before accessing fields
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit e626636e90)
2025-07-16 16:23:07 +02:00
Yiwei Zhang
41d9e42b27 meson: drop vdrm from virgl and venus
Currently neither virgl nor venus uses vdrm. One big blocker is neither
of them has adopted drm_syncobj yet.

Fixes: 1a6fc7006a ("meson: split subdir for virtio/vdrm and virtio/vulkan")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35933>
(cherry picked from commit 60eebe964d)
2025-07-16 16:23:06 +02:00
Eric Engestrom
b959f2416c meson: split subdir for virtio/vdrm and virtio/vulkan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35723>
(cherry picked from commit 1a6fc7006a)
2025-07-16 16:23:06 +02:00
Eric Engestrom
db3d2531cc virtio: move inc_virtio up one folder
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35723>
(cherry picked from commit 6f8c4a7ce1)
2025-07-16 16:23:06 +02:00
Eric Engestrom
ed07445ba4 .pick_status.json: Mark 485b520cf2 as denominated 2025-07-16 16:23:06 +02:00
Eric Engestrom
fe8dc9b6a6 .pick_status.json: Mark 0a581e7408 as denominated 2025-07-16 16:23:06 +02:00
Eric Engestrom
7edc8d913c .pick_status.json: Mark 94f42bb201 as denominated 2025-07-16 16:23:06 +02:00
Eric Engestrom
99011f4e8a .pick_status.json: Mark 2f5ff9788a as denominated 2025-07-16 16:23:06 +02:00
Eric Engestrom
3e1ea7faf3 .pick_status.json: Mark 6ad0b59cc8 as denominated 2025-07-16 16:23:06 +02:00
Eric Engestrom
29d50c5fdf .pick_status.json: Mark 85e4a19ed1 as denominated 2025-07-16 16:23:06 +02:00
Eric Engestrom
eb2f1e0858 .pick_status.json: Mark abe23e1cd0 as denominated 2025-07-16 16:23:06 +02:00
Eric Engestrom
0a76cf26dd .pick_status.json: Update to 5ee3c10d1e 2025-07-16 16:22:58 +02:00
Eric Engestrom
8a3d5aed64 docs: add sha sum for 25.1.5
Some checks failed
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2025-07-02 17:57:21 +02:00
Eric Engestrom
fe77ae26db VERSION: bump for 25.1.5 2025-07-02 17:46:17 +02:00
Eric Engestrom
1bf5e50bb2 docs: add release notes for 25.1.5 2025-07-02 17:46:17 +02:00
Rob Clark
1a85ddb514 rusticl: Fix work group size validation
For each dimension, we `threads *= lws`.. which is still zero if threads
is initialized to zero.

Fixes: eca4f0f632 ("rusticl/kernel: check that local size on dispatch doesn't exceed limits")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35864>
(cherry picked from commit 6bc47e65d7)
2025-07-02 16:55:02 +02:00
Rob Clark
9b3b65d7c3 freedreno/a6xx: Fix thread calc for dummy kernels
If a kernel uses no regs, max_reg will be -1.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35864>
(cherry picked from commit c417b83f19)
2025-07-02 16:55:02 +02:00
Boris Brezillon
d861a7b498 pan/layout: Fix size_B calculation for AFBC(3D)
Right now the headers are not counted when we calculate the total slice
size of an AFBC(3D) image. Fix that by special-casing size_B
initialization for AFBC.

I couldn't get back to the original commit introducing this mistakes,
so I'm flagging for backport instead of adding a proper Fixes tag.

Backport-to: 25.1
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35555>
(cherry picked from commit 1389a23708)
2025-07-02 16:19:33 +02:00
Iván Briano
61761d49d5 anv: move view_usage check to before setting the protected bit on it
Otherwise the comparison will always be false for protected content.

Also remove extra setting of the protected bit that was happening later.

Fixes: 8d9cc6aa23 ("anv: properly flag image/imageviews for ISL protection")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35870>
(cherry picked from commit 5b58b838fe)
2025-07-02 16:19:33 +02:00
Rhys Perry
27d61a6fd2 aco: update ctx.block when inserting discard block
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13432
Backport-to: 25.1
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35833>
(cherry picked from commit 21c4400278)
2025-07-02 16:19:32 +02:00
Jose Maria Casanova Crespo
09915f11a4 v3d: fix support for no buffer object bound
Piglit arb_texture_buffer_object-render-no-bo was generating
gpu resets because the uniform stream was missing the last
Fragment Shader uniform. So it was reading instead of the last
fragment shader uniform the first uniform of the vertex shader.

And using that unrelated VS uniform as the sampler address where
the texture should be read.

So now if a buffer object is not bound for a texture buffer object
we write the texture state base address to 0 (NULL) so the default
texture state is used.

So only is needed to set the 4 lower bits of the tmu_p0 with
the bit-mask of word enables.

Fixes: bb8285c258 ("v3d: add support for no buffer object bound")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35847>
(cherry picked from commit 0f8c681c5c)
2025-07-02 16:19:32 +02:00
Timothy Arceri
2ae8d0362b dri: fix __DRI_IMAGE_FORMAT* to PIPE_FORMAT* mappings
As per the old comment:

"These formats correspond to the similarly named MESA_FORMAT_*
 tokens, except in the native endian of the CPU.  For example, on
 little endian __DRI_IMAGE_FORMAT_XRGB8888 corresponds to
 MESA_FORMAT_XRGB8888, but MESA_FORMAT_XRGB8888_REV on big endian."

Fixes: 7e10601786 ("dri: Redeclare __DRI_IMAGE_FORMAT_* as PIPE_FORMAT_*")
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35814>
(cherry picked from commit 2ca46c7a7a)
2025-07-02 16:19:32 +02:00
Faith Ekstrand
b2186f35a1 nak: I/O offsets are unsigned when combined with RZ
Fixes dEQP-VK.pipeline.monolithic.descriptor_limits.compute_shader.samplers_16384

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35843>
(cherry picked from commit 3853f72f52)
2025-07-02 16:19:32 +02:00
Alyssa Rosenzweig
8bcc9c9a04 asahi: flush around XFB
this is required by the spec. fixes
gles-3.0-transform-feedback-uniform-buffer-object.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Backport-to: 25.1
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35802>
(cherry picked from commit 03a5b7f25c)
2025-07-02 16:19:32 +02:00
Jesse Natalie
fe9d475e34 dzn: Roll up initialization failure in dzn_meta_init
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13416
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35748>
(cherry picked from commit 7f4ae75903)
2025-07-02 16:19:32 +02:00
Rhys Perry
a20567eead nir/lower_bit_size: fix bitz/bitnz
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 6585209cdd ("nir/lower_bit_size: mask bitz/bitnz src1 like shifts")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35770>
(cherry picked from commit 08859cbe50)
2025-07-02 16:19:32 +02:00
Faith Ekstrand
dd65919d84 nak: Tell NIR to lower invalid implicit LODs
I think NVIDIA hardware more or less does this for us for free but it's
nice to have NIR make sure.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35795>
(cherry picked from commit c6ad70551b)
2025-07-02 16:19:32 +02:00
Dave Airlie
0124b9a342 nouveau: workaround linear/z rendering interaction
nvidia hardware can't render to linear surfaces except under some
very limited circumstances, one of those is if Z is enabled.

However there appears to be some combination of gnome-shell, and
prime (with 2 nouveau cards) where we end up getting through the
GL API to the situation where we try this. This in a production
build causes the kernel to crash with a GR error.

However there existed a period of time where the hw/kernel due to
some other random hw misconfiguration didn't crash when this happened
and doing this was prefect fine. (linear + tiled Z).

This restores the userspace code to do this and just ignores the
Z buffers if we are asked for linear rendering, and seems sufficient
to fix the problem.

I do understand this is a workaround, but I think it's reasonable to
add to the nouveau GL driver at this time since we don't want to
maintain if for ever and it probably should fix a bunch of wierd
user problems with multi gpu and nouveau.

Cc: mesa-stable
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35221>
(cherry picked from commit 06e8db646a)
2025-07-02 16:19:32 +02:00
Jose Maria Casanova Crespo
78dbc63715 v3d: Avoid fast TLB blit if reused job doesn't store the color buffer
Fixes: 66de8b4b5c ("v3d: add a faster TLB blit path")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35739>
(cherry picked from commit d0163f1096)
2025-07-02 16:19:32 +02:00
Calder Young
e09031bbd3 anv: Fix typo when checking format's extended usage flag
Fixes: f4c1753c1a ("anv: report color/storage features on YCbCr images with EXTENDED_USAGE")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35703>
(cherry picked from commit 646977348b)
2025-07-02 16:19:32 +02:00
Yiwei Zhang
fec4040ada venus: fix msaa state sample location info sanitization
The additional reference has corrupted the below D/S state instead of
properly ending the msaa state pnext chain.

Fixes: ff64092ff3 ("venus: support VK_EXT_sample_locations")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35808>
(cherry picked from commit cb54338f65)
2025-07-02 16:19:32 +02:00
David Rosca
2089eaa39e frontends/va: Fix SyncSurface when used to sync coded buffer
This would skip the coded buffer fence wait if the surface fence is NULL.

Fixes: 0f20a3a4f1 ("frontends/va: Add surface pipe_fence for vl_compositor rendering")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35782>
(cherry picked from commit 53e3e44eb3)
2025-07-02 16:19:32 +02:00