Commit graph

119900 commits

Author SHA1 Message Date
Jason Ekstrand
769d6ba200 anv: Use TRANSFER_SRC_OPTIMAL for depth/stencil MSAA resolves
As of 52ad1712ed, TRANSFER_SRC_OPTIMAL and SHADER_READ_ONLY_OPTIMAL
are now identical for depth buffers so there's no reason why we need to
use the "wrong" layout.  Technically, according to Vulkan, blits and
MSAA resolves are transfer ops so we should use the transfer layout now
that we can.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
2020-01-24 17:42:36 +00:00
Jason Ekstrand
71c0f9e76d intel/blorp: resize src and dst surfaces separately
When copying to an RGB surface, we treat it as an R only one of three
times the width, which may end up being larger than the maximum size
supported by the hardware and so it hits the shrink path. This forced
both source and destination surfaces to be shrunk, even though it's not
necessary for the former, and may even hit some assertions in some
cases, such as the surface being compressed.

Fixes several tests under dEQP-VK.api.copy_and_blit.core.image_to_image.dimensions.*

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3422>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3422>
2020-01-24 17:02:40 +00:00
Samuel Pitoiset
918f00eef8 aco: combine MRTZ (depth, stencil, sample mask) exports
Instead of emitting up to 3 for each different components (depth,
stencil and sample mask). This is needed to fix a hw bug on GFX6.

Totals from affected shaders:
SGPRS: 34728 -> 35056 (0.94 %)
VGPRS: 26440 -> 26476 (0.14 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1346088 -> 1344180 (-0.14 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 3922 -> 3915 (-0.18 %)
Wait states: 0 -> 0 (0.00 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3538>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3538>
2020-01-24 16:42:15 +00:00
Timur Kristóf
c787b8d2a1 aco/gfx10: Fix VcmpxExecWARHazard mitigation.
The SOPP instruction shouldn't have a definition, and its block
should be set to -1 in order to prevent it from being recognized
as a branch.
Also fix a typo in the readme.

Fixes: d6dfce02d0
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3552>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3552>
2020-01-24 16:21:08 +00:00
Timur Kristóf
8a32f57fff aco: Transform uniform bitwise instructions to 32-bit if possible.
This allows removing superfluous s_cselect instructions
that come from turning booleans into 64-bit vector condition.

v2 by Daniel Schürmann:
- Make the code massively simpler
v3 by Timur Kristóf:
- Fix regressions, make it work in wave32 mode
- Eliminate extra moves by not always using the SCC definition
- Use s_absdiff_i32 for uniform XOR
- Skip the transformation for uncommon or invalid instructions

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3450>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3450>
2020-01-24 14:40:45 +00:00
Martin Fuzzey
d1925fec53 etnaviv: update Android build files
etnaviv no longer builds on Android, fix this.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3447>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3447>
2020-01-24 14:03:28 +00:00
Rhys Perry
b046f55086 aco: use nir_move_copies
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
72e9a23443 radv/aco: use ACO for GS copy shaders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
f8f7712666 aco: implement GS copy shaders
v5: rebase on float_controls changes
v7: rebase after shader args MR and load/store vectorizer MR

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
de4ce66f5c aco: remove needs_instance_id
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
e192e268de aco: explicitly mark end blocks for exports
For GS copy shaders, whether we want to do exports is conditional. By
explicitly marking the end blocks, we can mark an IF's then branch as an
export block and ensure that's where the assembler inserts null exports.

v6: only fixup exports in the end block, like before
v8: simplify some code

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
d46a54ecff radv/aco: allow ACO for GS
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
8bad100f83 aco: implement GS on GFX7-8
GS is the same on GFX6, but GFX6 isn't fully supported yet.

v4: fix regclass
v7: rebase after shader args MR

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
40bb81c9dd radv/aco,aco: implement GS on GFX9+
v2: implement GFX10
v3: rebase
v7: rebase after shader args MR
v8: fix gs_vtx_offset usage on GFX9/GFX10
v8: use unreachable() instead of printing intrinsic
v8: rename output_state to ge_output_state
v8: fix formatting around nir_foreach_variable()
v8: rename some helpers in the scheduler
v8: rename p_memory_barrier_all to p_memory_barrier_common
v8: fix assertion comparing ctx.stage against vertex_geometry_gs

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
70f63c1988 aco: improve support for s_sendmsg
In particular, the messages needed for GS.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
0da7b3b18b radv: move gs copy shader creation before other variants
ACO lowers output derefs which breaks the shader_info pass used by gs copy
shader creation.

v3: rebase

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Timur Kristóf
23edcf6490 aco: Make a better guess at which instructions need the VCC hint.
Previously, bool_to_vector_condition would always set the VCC hint
on its result. This commit improves it by having the optimizer set
the VCC hint only when the result really needs to be in the VCC.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3451>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3451>
2020-01-24 13:14:23 +00:00
Jan Zielinski
83f24b0587 gallium/swr: implementation of tessellation shaders compilation
TCS and TES shaders compilation mechanisms in SWR and state
management implementation.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484>
2020-01-24 11:38:03 +00:00
Bas Nieuwenhuizen
0890482969 radv: Allow DCC & TC-compat HTILE with VK_IMAGE_CREATE_EXTENDED_USAGE_BIT.
I misunderstood the flag when initially disabling. But this flag
only does something with mutable formats. If we have DCC and
mutable formats, the formats are close enough that the allowed
usage flags are not meaningfully different nor used during
allocation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3424>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3424>
2020-01-24 11:16:39 +00:00
Bas Nieuwenhuizen
1b447bd2e6 radv: Expose VK_KHR_swapchain_mutable_format.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2354
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3425>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3425>
2020-01-24 10:47:07 +00:00
Connor Abbott
b103157a0e freedreno: Document CP_INDIRECT_BUFFER_CHAIN
This will let us use batch chaining instead of growing batches on a5xx
and a6xx.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
2020-01-24 10:03:08 +00:00
Connor Abbott
f58242b56e freedreno: Document CP_UNK_A6XX_55
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
2020-01-24 10:03:08 +00:00
Connor Abbott
3cf1d6b8db freedreno: Document CP_COND_REG_EXEC more
The vulkan blob uses the RENDER_MODE mode to condition a blit on the
render mode in traces of a dEQP triangle test.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182>
2020-01-24 09:23:27 +00:00
Samuel Pitoiset
a31bcf2be6 ac/llvm: fix missing casts in ac_build_readlane()
Because ac_build_optimization_barrier() overwrites the original
src_type, we have to keep track of it before emitting that barrier.
Otherwise, wrong conversions are expected for pointers or small
bitsizes.

By doing this, we no longer need to do the cast dance in
ac_build_readlane_no_opt_barrier(), it was just necessary for
ac_build_optimization_barrier().

This fixes a bunch of crashes with subgroups related tests when
RADV_DEBUG=checkir is enabled, and it also fixes a compiler crash
with The Surge 2.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2395
Fixes: 0f45d4dc2b ("ac: add ac_build_readlane without optimization barrier")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3535>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3535>
2020-01-24 07:40:07 +01:00
Jason Ekstrand
8a135ff6e5 anv/apply_pipeline_layout: Initialize the nir_builder before use
Fixes: #2410
Fixes: 3c754900b5 "nir: don't emit ishl in _nir_mul_imm() if backend doesn't support bitops"
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3548>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3548>
2020-01-23 19:35:39 -08:00
Kenneth Graunke
adaa3583f5 meson: Prefer 'iris' by default over 'i965'.
This changes the default driver for Intel Gen8-11 hardware to be
the newer 'iris' driver rather than the older 'i965' driver.  To
continue using i965, pass -Dprefer-iris=false when building.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3540>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3540>
2020-01-23 15:34:54 -08:00
Adam Jackson
2fc11e8a05 drisw: Cache the depth of the X drawable
This is not always ->rgbBits, because there are cases where that could
be 32 but we're (legally) bound to a depth-24 pixmap. The important
thing to have match here is the actual server-side notion of depth.  You
can look this up (at modest expense) from the xlib visual info if the
fbconfig has a visual. But it might not, so if not, fetch it (at
slightly greater expense) from XGetGeometry. Do this at GLX drawable
creation so you don't have to do it on the SwapBuffers path.

Apparently this fixes glx/glx-swap-singlebuffer, which is unintentional
but quite pleasant.

Fixes: mesa/mesa#2291
Fixes: 90d58286 ("drisw: Fix and simplify drawable setup")
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3305>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3305>
2020-01-23 23:03:13 +00:00
Eric Anholt
59f29fc845 turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.
There are only a couple of hard cases left using pkt4, where the register
number to write is computed.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Eric Anholt
d67100519e turnip: Convert renderpass setup to the new register packing macros.
This gets a lot of the hard code converted over to the new macros,
resulting in (I feel) much more readable code with
LESS_SHOUTING_ABOUT_THE_REG().  I decided to consistently put the reg on
its own line, so that all the register names line up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Eric Anholt
08837ea3d2 turnip: Port krh's packing macros from freedreno to tu.
This introduces some minor unpacking of the temporary fd_reg_pair structs
to code that previously was packing a whole register field.

In the pack wrapper in tu_cs.h, I added some explanatory docs, dropped the
relocs handling since we don't need it, and removed the extra regs[] in
the __ONE_REG() macro (which was causing gcc's optimizer to fall on its
face in my release build).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Eric Anholt
d4bc3c93ea freedreno: Fix OUT_REG() on address regs without a .bo supplied.
Sometimes you want to zero out an address by supplying a NULL BO, but
without this we would end up only emitting one dword.  Increases size of
fd6_gmem.o by .8%, though it's not clear to me why (no obvious terrible
codegen happening)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Eric Anholt
c1327bc283 freedreno: Add some missing a6xx address declarations.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Ian Romanick
4b7de92e5f relnotes: Add GL_INTEL_shader_integer_functions2 and VK_INTEL_shader_integer_functions2
Suggested-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-01-23 13:36:14 -08:00
Vasily Khoruzhick
beab31b9bb lima: use imul for calculations with intrinsic src
It's source is supposed to be int, so we have to use integer
multiplication otherwise we'll get undefined result.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3529>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3529>
2020-01-23 21:16:22 +00:00
Vasily Khoruzhick
3c754900b5 nir: don't emit ishl in _nir_mul_imm() if backend doesn't support bitops
Otherwise we'll have to lower it later.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3529>
2020-01-23 21:16:22 +00:00
Icecream95
cf2c5a56a1 pan/decode: Rotate trace files
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
c1952779d6 pan/decode: Dump to a file
The file name is taken from the environment variable
PANDECODE_DUMP_FILE, defaulting to pandecode.dump if it is not set.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
be22c0789f pan/decode: Support dumping to a file
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
20a8957397 pan/bifrost: Support disassembling to a file
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
968f36d1fc pan/midgard: Support disassembling to a file
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
7b525ba02b pan/midgard: Fix a memory leak in the disassembler
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Eric Anholt
fbd9b4ce08 turnip: Fix execution of secondary cmd bufs with nothing in primary.
We want to finish off cmd emission in the primary CS and add its entry to
the IB, but regardless of whether there had been anything in the primary
CS to emit, we still need a reserved CS entry for the loop below.

Fixes crashes in dEQP-VK.binding_model.shader_access.secondary_cmd_buf.*
and many more in dEQP-VK.renderpass*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3524>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3524>
2020-01-23 20:27:26 +00:00
Alyssa Rosenzweig
d6d6ef2862 panfrost: Drop mysterious zero=0xFFFF field
It doesn't seem to affect any results and it's not at all clear if/why
the blob sometimes(?) sets it? So let's clean this up since this
solution isn't correct anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3513>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3513>
2020-01-23 19:59:58 +00:00
Icecream95
f8eb4441ae pan/midgard: Fix bundle dynarray leak
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3496>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3496>
2020-01-23 19:35:09 +00:00
Marek Olšák
43d9bac6f2 radeonsi: separate LLVM compilation from non-LLVM code
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
1a0890dcf3 radeonsi: change prototypes of si_is_multi_part_shader & si_is_merged_shader
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
7ce84b256e radeonsi: make si_compile_shader return bool
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
be772182e0 radeonsi: make si_compile_llvm return bool
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
bd19d144a1 radeonsi: move more LLVM functions into si_shader_llvm.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
9a66f3d3e2 radeonsi: fold si_shader_context_set_ir into si_build_main_function
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00