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aco/gfx10: Fix VcmpxExecWARHazard mitigation.

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The SOPP instruction shouldn't have a definition, and its block
should be set to -1 in order to prevent it from being recognized
as a branch.
Also fix a typo in the readme.

Fixes: d6dfce02d0
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3552>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3552>
This commit is contained in:
Timur Kristóf 2020-01-24 15:17:44 +01:00 • committed by Marge Bot
parent 8a32f57fff
commit c787b8d2a1
2 changed files with 2 additions and 3 deletions
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1
src/amd/compiler/README.md
View file

@ -154,7 +154,6 @@ A VALU instruction or an `s_waitcnt vmcnt(0)` between the two instructions.
Triggered by:
An SMEM instruction reads an SGPR. Then, a VALU instruction writes that same SGPR.
Despite LLVM
Mitigated by:
Any non-SOPP SALU instruction (except `s_setvskip`, `s_version`, and any non-lgkmcnt `s_waitcnt`).

4
src/amd/compiler/aco_insert_NOPs.cpp
View file

@ -491,9 +491,9 @@ void handle_instruction_gfx10(Program *program, NOP_ctx_gfx10 &ctx, aco_ptr<Inst
ctx.has_nonVALU_exec_read = false;
/* Insert s_waitcnt_depctr instruction with magic imm to mitigate the problem */
aco_ptr<SOPP_instruction> depctr{create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt_depctr, Format::SOPP, 0, 1)};
aco_ptr<SOPP_instruction> depctr{create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt_depctr, Format::SOPP, 0, 0)};
depctr->imm = 0xfffe;
depctr->definitions[0] = Definition(sgpr_null, s1);
depctr->block = -1;
new_instructions.emplace_back(std::move(depctr));
} else if (instr_writes_sgpr(instr)) {
/* Any VALU instruction that writes an SGPR mitigates the problem */