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Author SHA1 Message Date
David Rosca
5e7b6df860 radv/video: Support quantization map on VCN5
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VCN5 needs to convert the input map image to internal format.

Reviewed-by: Autumn Ashton <misyl@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37156>
 2025-09-08 10:52:06 +00:00
David Rosca
a03e055cd3 radv/video: Set rate control to default on reset 
If we never get rate control info, we would treat it as rate control
disabled and use QP value from slice info which is always 0 for default
rate control.

Cc: mesa-stable
Reviewed-by: Autumn Ashton <misyl@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37156>
 2025-09-08 10:52:05 +00:00
David Rosca
070c3d2b89 ac/vcn: Add RADEON_VCN_IB_COMMON_OP_RESOLVEINPUTPARAMLAYOUT 
Reviewed-by: Autumn Ashton <misyl@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37156>
 2025-09-08 10:52:05 +00:00
Faith Ekstrand
446d5ef103 vulkan: Drop the driver_internal from vk_image_view_init/create() 
It alwways comes in through the create flags now.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36957>
 2025-09-05 23:34:14 +00:00
Faith Ekstrand
1897d5d9c9 radv: Use VK_IMAGE_VIEW_CREATE_DRIVER_INTERNAL_BIT_MESA 
This does mean having to set the flag everywhere, which is a bit
annoying, but I don't think I missed any.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36957>
 2025-09-05 23:34:12 +00:00
Timur Kristóf
78efa4157a radv: Don't use V_370_PFP or V_028A90_PS_DONE on compute queues 
The compute queue doesn't support these things.
This change doesn't fix any known issues, but better to be safe.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
 2025-09-05 13:42:56 +00:00
Timur Kristóf
8447a4bfca radv: Clean up use of RELEASE_MEM on GFX7 MEC 
MEC probably doesn't support EVENT_WRITE_EOP.
Both PAL and RadeonSI use RELEASE_MEM.

RADV used RELEASE_MEM too but "is_gfx8_mec" was very misleading.
This commit just cleans that up. No functional changes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
 2025-09-05 13:42:56 +00:00
Timur Kristóf
c56c746b71 radv: Don't use EVENT_WRITE_EOS on GFX7 
EOS events are buggy on GFX7 and can cause hangs when used
together in the same IB with CP DMA packets that use L2.
While we don't use the L2 for CP DMA copies, we still use it
with CP DMA prefetches, so the issue needs to be mitigated.

As a mitigation, avoid using EVENT_WRITE_EOS and prefer to use
the BOTTOM_OF_PIPE event instead of PS_DONE/CS_DONE, which should
be close enough.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
 2025-09-05 13:42:56 +00:00
Timur Kristóf
2f587ea8be radv: Don't set SWITCH_ON_EOI without tessellation 
For reference, see si_get_init_multi_vgt_param.
The SWITCH_ON_EOI bit is only needed with tessellation.

Also remove some useless lines.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
 2025-09-05 13:42:56 +00:00
Timur Kristóf
e8d1e935fb radv/amdgpu: Don't use IB2 on GFX6 (for now) 
GFX6 actually supports IB2, but doesn't support chaining between
chunks inside the IB2. See WaCpIb2ChainingUnsupported in PAL.

Disable IB2 on GFX6 for now.

The proper fix will be to disable use_ib in just secondary
command buffers on GFX6 and emit multiple IB2 packets in the
main command buffer. This will be implemented later.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
 2025-09-05 13:42:56 +00:00
Timur Kristóf
3056279d09 radv/amdgpu: Use correct NOP packets when unchaining a CS 
GFX6 doesn't support single-dword PKT3 NOP packets,
so they shouldn't be used when unchaining a CS.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
 2025-09-05 13:42:56 +00:00
Timur Kristóf
132a61c6b7 radv/amdgpu: Fix crash with RADV_DEBUG=noibs 
After a refactor last year, the noibs option stopped working
because it hits an assertion when empty IBs are submitted.

Emit a single large NOP packet to avoid submitting empty IBs.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
 2025-09-05 13:42:56 +00:00
Christoph Pillmayer
f81f3c85e2 nir/opt_algebraic: Convert a + b + a to b + 2a
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This allows fusing into one FMA later.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37113>
 2025-09-05 11:39:51 +00:00
Samuel Pitoiset
8233d9d571 radv: rename RADV_CMD_DIRTY_FS_STATE to RADV_CMD_DIRTY_PS_STATE
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It's called PS everywhere else.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37087>
 2025-09-05 10:16:20 +00:00
Samuel Pitoiset
f180682441 radv: add a new dirty bit for emitting a PS epilog 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37087>
 2025-09-05 10:16:19 +00:00
Samuel Pitoiset
211e0823ec radv: add a new dirty bit for compiling/binding a PS epilog 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37087>
 2025-09-05 10:16:18 +00:00
Samuel Pitoiset
11e5f86a94 radv: add a function to bind a PS epilog 
The idea would be to separate compiling and emitting PS epilog in
two separate states.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37087>
 2025-09-05 10:16:17 +00:00
Samuel Pitoiset
bc71787ea3 radv: remove unnecessary NULL check when creating PS epilogs 
It's already checked in the caller.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37087>
 2025-09-05 10:16:15 +00:00
Samuel Pitoiset
d771f2c462 radv: add small helper to dispatch RT 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37141>
 2025-09-05 09:21:26 +00:00
Samuel Pitoiset
1b6aad9def radv/meta: use radv_CmdDispatchBase() directly for ASTC decode 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37141>
 2025-09-05 09:21:25 +00:00
Samuel Pitoiset
8ddb06f6e0 radv: trigger VS related states in radv_bind_pre_rast_shader() 
No need to duplicate this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37141>
 2025-09-05 09:21:24 +00:00
Samuel Pitoiset
c589097999 radv: determine which shader is the last VGT shader using next stage 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37141>
 2025-09-05 09:21:23 +00:00
Samuel Pitoiset
9a93c7c243 radv: simplify sample shading state tracking 
Sample shading can be enabled with PSO or with fragment shaders, but
only the PSO state is bound because it's still possible to access
the FS everywhere during cmdbuf recording.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37141>
 2025-09-05 09:21:22 +00:00
Samuel Pitoiset
cb9c25cbea radv: rename radv_flush_occlusion_query_state() 
To match other emit functions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37141>
 2025-09-05 09:21:21 +00:00
Samuel Pitoiset
7f12f98741 radv: rework the optimal packet order for dispatches 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37013>
 2025-09-05 07:28:14 +00:00
Samuel Pitoiset
62c92a0516 radv: rework the optimal packet order for task/mesh draws 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37013>
 2025-09-05 07:28:13 +00:00
Samuel Pitoiset
f5bbe5228f radv: rework the optimal packet order for "normal" draws 
This idea comes from RadeonSI but RADV was already implementing
something similar. Except that it checked for wait-for-idle but this
shouldn't be necessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37013>
 2025-09-05 07:28:12 +00:00
Samuel Pitoiset
f289e8eddc radv: only expose permitted global queue priorities
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It's the responsability of the application to check for
VK_ERROR_NOT_PERMITTED, but filtering not permitted priorities seems
better.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13775
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37076>
 2025-09-05 06:34:36 +00:00
Samuel Pitoiset
43cba046e6 radv/amdgpu: add a function to query permitted context priorities 
The only way I know of is to create a context to verify if a priority
is permitted or not.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37076>
 2025-09-05 06:34:36 +00:00
Samuel Pitoiset
57deff5658 radv: fix vk_error in radv_update_preambles() 
This needs to be a vk object, otherwise it asserts or crashes.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37179>
 2025-09-05 06:14:49 +00:00
Samuel Pitoiset
44541e84e9 radv: move misc related drirc to radv_drirc::misc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:17 +00:00
Samuel Pitoiset
8e4d5743d2 radv: move debug related drirc to radv_drirc::debug 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:17 +00:00
Samuel Pitoiset
f13b181791 radv: move performance related drirc to radv_drirc::performance 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:16 +00:00
Samuel Pitoiset
d575b91b3a radv: move features related drirc to radv_drirc::features 
For better organization.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:16 +00:00
Samuel Pitoiset
d915f24cb2 radv: move drirc options to a separate struct 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:15 +00:00
Samuel Pitoiset
d98e31eab6 radv: mark RADV_DEBUG=nongg_gs as deprecated 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:15 +00:00
Samuel Pitoiset
7304423b5c radv: mark RADV_DEBUG=splitfma as deprecated 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:14 +00:00
Samuel Pitoiset
4748ecb238 radv: mark RADV_DEBUG=invariantgeom as deprecated 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:13 +00:00
Samuel Pitoiset
a8a8bfee1f radv: mark RADV_DEBUG=nodynamicbounds as deprecated 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:13 +00:00
Georg Lehmann
83326af899 nir/builder: add nir_inverse_ballot_imm 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37178>
 2025-09-04 14:03:56 +00:00
Georg Lehmann
ef8c364d3d nir: make inverse_ballot 1bit only 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37178>
 2025-09-04 14:03:56 +00:00
Eric Engestrom
d698251e32 radv/ci: document whether ci-tron jobs runs on an APU or a dGPU 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37124>
 2025-09-04 09:47:21 +00:00
Eric Engestrom
1a1e21e725 radv/ci: deduplicate navi10 GPU_VERSION 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37124>
 2025-09-04 09:47:21 +00:00
Yiwei Zhang
94d8a4a465 radv: bind aliased wsi image at memory offset zero 
This aligns with common wsi, and also obeys dedicated alloc requirement.

Fixes: 825c05a7e8 ("radv: adopt wsi_common_get_memory")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37152>
 2025-09-03 16:29:34 +00:00
Rhys Perry
7f5c84d7ac radv: fix shift overflow in radv_pipeline_init_dynamic_state 
Fixes UBSan error with thewitness/005aa77325a11410:
runtime error: left shift of 15 by 28 places cannot be represented in type 'int'

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37055>
 2025-09-03 11:47:00 +00:00
Rhys Perry
1105f7b98f aco: fix signed integer overflow 
Fix UBSan error:
runtime error: signed integer overflow: 2147483647 + 32 cannot be represented in type 'int'

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37055>
 2025-09-03 11:47:00 +00:00
Samuel Pitoiset
6bc70a0e8f radv/ci: remove RADV_DEBUG=novideo for radv-gfx1201-vkcts
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37134>
 2025-09-03 07:19:55 +00:00
Samuel Pitoiset
3cb77cb144 radv/rt: fix a potential issue with RADV_PERFTEST=dmashaders 
Shaders must be synchronized before doing anything.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37126>
 2025-09-03 06:16:14 +00:00
Samuel Pitoiset
decf9af472 radv/rt: only use one user SGPR for the traversal shader addr 
All shaders are allocated in the 32-bit addr space. To avoid an issue
with alignment, and also for future work, there is an unused user SGPR.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37133>
 2025-09-03 05:53:41 +00:00
Daniel Schürmann
fcf8899c9e radv/rt: use ACCESS_CAN_REORDER when loading SBT entries 
Totals from 56 (0.07% of 79839) affected shaders: (Navi48)

Instrs: 2790220 -> 2790130 (-0.00%); split: -0.00%, +0.00%
CodeSize: 14704952 -> 14704292 (-0.00%)
Latency: 13994383 -> 13953444 (-0.29%); split: -0.29%, +0.00%
InvThroughput: 2717973 -> 2710748 (-0.27%); split: -0.27%, +0.00%
VClause: 68783 -> 68687 (-0.14%)
SClause: 51910 -> 52007 (+0.19%)
Copies: 223192 -> 223190 (-0.00%); split: -0.01%, +0.01%
VALU: 1557513 -> 1557451 (-0.00%); split: -0.00%, +0.00%
VMEM: 118789 -> 118692 (-0.08%)
SMEM: 66498 -> 66595 (+0.15%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36933>
 2025-09-02 19:07:30 +00:00