match_expression() only accesses the first instr->def.num_components
elements, so we don't need to ensure the rest are zero.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39808>
The spec recommends the capture/replay enabled buffers to be separated
from other buffers created by the implementation, so this introduces a
split-heap mode to be used only when this feature is enabled.
The rest of the change is trivial, as we can allocate from the
fixed-heap on BDA-C/R-enabled allocations during capture, and simply
map the address we're given on that same heap during replays.
Architectures older than v10 use AUTO_VA, so we can't do the same thing
on them.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38871>
Add a check to ensure that when load_const can be narrowed, the bit size
from other widening conversion sources must be 16-bit to maintain
consistency across all phi sources.
Signed-off-by: jiajia Qian <jiajia.qian@nxp.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39773>
[WHY]
To read back register read/write counts from VPEs, we need to add a new
wrapper function.
[HOW]
Added a wrapper that calls build command and populate the register
profiling data structure.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
The embedded-buffer usage decision should be based on the stream's 3DLUT
mode rather than a loosely defined tm_enabled boolean.
[HOW]
- Replace cmd_info.tm_enabled with cmd_info.lut3d_type
- Add vpe_get_stream_lut3d_type() helper and use it in cmd info/buffer req
- Prefix internal helpers (vpe_calculate_scaling_ratios, vpe_should_generate_cmd_info)
Signed-Off-by: Farhan Rouf <Farhan.Rouf@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[HOW]
- Re-order the function pointer assignments to have the same order as
defined.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-Off-by: Navid Assadian <Navid.Assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
The packet header has uninitialized fields that can introduce 1b'1 in
reserved bits.
[HOW]
initialize the header to 0
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Roy Chan <Roy.Chan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Multiplication result may overflow int before it is converted to long
long
[HOW]
Updated the expression to avoid possible overflow
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Support different generations of swizzle mode.
[HOW]
Added different swizzle mode parameters for supporting plane
description.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Ricky Lin <Ricky.Lin@amdeng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Fast load support is required for 3DLUT and Shaper features.
The calculation logic needs to be modularized and exposed via
the resource interface to support this.
[HOW]
1. Add `calculate_shaper` and `program_fastload` function pointers to the `resource` struct.
2. Move shaper normalization, HDR multiplier update, and 3DLUT update logic from
`vpe_color_update_movable_cm` into a new core function `vpe_calculate_shaper`.
3. Implement `vpe10_calculate_shaper` and assign it to the resource function table for VPE10 and VPE11.
4. Update `vpe_create_engine` return signature to remove `const` qualifier.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Nawwar Ali <Nawwar.Ali@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Reg_update macro and its lastWritten_value design are static global
variables and cannot support multi-thread usage
[HOW]
remove reg_update usage and combine the separated calls together
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
This is necessary for GetPipelineExecutablePropertiesKHR, RADV_DEBUG and
fossil-db.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39827>
Having them in GTT makes read back fast but it also affects performance
a lot. Now that a staging buffer can be used for read back, we can
switch to VRAM without drawbacks.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39194>
pipe_aligned_buffer_create can allow allocate 4GB but that's large enough
for now.
PIPE_USAGE_STREAM is used for now to keep the 2 BOs in GTT.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39194>
This will allow to use a staging buffer to copy the sqtt data
without moving away the BO from VRAM (without this change,
the vram->staging copy won't be executed since we're in the
middle of a flush).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39194>
Given a situation like this :
- CB_A: begin, renderDepthA, end
- CB_B: begin, computeA, barrier (depth), computeB, end
The depth cache is not being flushed between renderDepthA & computeB
because :
- it's not flushed at the end of CB_A (it's not required)
- when CB_B starts, we're still on GFX pipeline mode but do not
flush render caches because pipeline mode is unknown
- when barrier is CB_B is executed, we're already in compute
pipeline mode and HW cannot flush depth.
The fix is to flush RT/depth cached when switching from unknown
pipeline mode any pipeline mode.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e6dae6ef5f ("vulkan: Optimize implicit end_subpass barrier")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14816
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Tested-by: David Gow <david@davidgow.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39824>
Now that we have a solid logic for caching meta objects, trying to
reduce the number of format variants isn't super useful. In practice,
the shaders would be cached on disk, so this would only allocate few
more bytes for the meta objects.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39786>
The Vulkan spec says:
"Store and resolve operations are only performed at the end of a
render pass instance that does not specify the
VK_RENDERING_SUSPENDING_BIT_KHR flag."
VK_RENDERING_SUSPENDING_BIT is also illegal with custom resolves.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
This is mostly for not calling CmdBeginRendering() while rendering
is already active in order to catch potential driver issues. This
requires a small refactoring of how the rendering info is passed for
resolves though.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
This bit is set in mocs for other protected attachment types by
anv_image_fill_surface_state() however was ommited for depth/stencil
attachments here.
Without the protected bit set, it causes heavy black artifacting when
attaching a protected depth attachment image to a framebuffer.
Fixes: 794b0496e9 ("anv: enable protected memory")
Signed-off-by: Juston Li <justonli@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39818>
The Panfrost hardware already supports controlling ASTC decode
precision via the Decode Wide plane descriptor field. Wire up the
Vulkan extension by parsing VkImageViewASTCDecodeModeEXT from the
image view pNext chain and setting astc.narrow when the application
requests VK_FORMAT_R8G8B8A8_UNORM decode mode.
The extension is limited to v9+ since the ASTC plane descriptors
with Decode Wide/HDR fields only exist from Valhall onwards.
decodeModeSharedExponent is not supported.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39799>
The destination for CmdResolve can be a 3D image, and while some
restrictions on the base layer and count exist, the Z offset into which
the resolve will happen has no such restriction.
Fixes some new tests: dEQP-VK.pipeline.*.multisample.m10_resolve.resolve_cmd.*.full_3d.*
Fixes: 0e7761b35cd ("anv, hasvk: allow using a 3D image as a resolve target")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39793>
