Commit graph

17 commits

Author SHA1 Message Date
Alyssa Rosenzweig
941c37c085 nir/lower_idiv: Remove imprecise_32bit_lowering
NIR has two implementations of lower_idiv, keyed on the
imprecise_32bit_lowering flag. This flag is misleading: the results when
setting this flag "imprecise", they're completely wrong for some values.
If a backend has a native implementation of umul_high, the correct path
isn't that much more expensive. If it doesn't, it's substantially slower
for highp integer divison... but in practice, non-constant highp integer
division is pretty rare.

After a painful migration of the tree, this code path has no more users.
Remove it so nobody else gets the bright idea of using it again.

Closes: #6555
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19303>
2022-10-27 19:37:14 +00:00
Yusuf Khan
d9a257b339 nv50/ir: nir_op_b2i8 and nir_op_b2i16
Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19256>
2022-10-27 02:16:24 +00:00
Thomas Debesse
6d5921c623 nv50: call nir_lower_flrp
Fix #7432: unknown nir_op flrp assertion

This copy-pastes src/gallium/drivers/radeonsi/si_shader_nir.c

The lower_flrp16 value differs given chipset >= NVISA_GV100_CHIPSET.

Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19003>
2022-10-10 17:22:49 +00:00
Danilo Krummrich
6a9825bc1b nv50/ir/nir: always round towards zero for f2i/f2u
Conversions to integers must be rounded towards zero, hence, actually
do this for all integers including 8/16 bit sources.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Danilo Krummrich <dakr@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18109>
2022-09-09 17:32:18 +02:00
Danilo Krummrich
109d56f612 nv50/ir/nir: convert 8/16 bit src to 32 bit for {i,u}2f64
Converting signed and unsigned integers from 8/16 bit sources to a 64 bit
floating point destination (i2f64 / u2f64) isn't possible, hence convert
the source to 32 bit first.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Danilo Krummrich <dakr@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18109>
2022-09-09 17:32:16 +02:00
Danilo Krummrich
ec60dcd870 nv50/ir/nir: avoid 8/16 bit dest regs for OP_MOV
Instructions like

  mov u16 %r78s 0x00ff (0)

are dropped, since they're not supported by the HW, hence avoid using
8/16 bit destination registers for OP_MOV and use the full width of the
register instead.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Danilo Krummrich <dakr@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18109>
2022-09-09 17:32:10 +02:00
Danilo Krummrich
6e2fda15f1 nv50/ir/nir: convert to 32 bit for all OP_SET opcodes
The 'set' instruction does distinguish between signed and unsigned, but
always treats values as 32 bit. For singed values < 0 with a bit width
smaller than 32 bit this falsely results in treating it as a positive
value.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Danilo Krummrich <dakr@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18109>
2022-09-09 17:32:05 +02:00
Danilo Krummrich
cd53bcd325 nv50/ir/nir: add conversion ops for bit width < 32
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Danilo Krummrich <dakr@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18109>
2022-09-09 17:31:57 +02:00
M Henning
f90f04d501 nv/nir: Set ssbo CacheMode from intrinsic access
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18354>
2022-09-04 20:32:30 +00:00
Pierre Moreau
16b07b342d nv50/nir: A group barrier is CTA-level not global-level
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10711>
2022-08-23 18:29:44 +00:00
Emma Anholt
f6c5b1d6c6 nir: Split usub_sat lowering flag from uadd_sat.
Intel vec4 would like to do uadd_sat, but use lowering for usub_sat.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17637>
2022-07-22 17:54:28 +00:00
M Henning
4ee6345d2e nouveau: Drop C++03 compat code
Mesa as a whole requires C++14 nowadays, so this isn't needed any more.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17307>
2022-07-05 13:23:12 +00:00
Emma Anholt
1e2e52eff7 nouveau/nir: Implement mul_zero_wins behavior for use_legacy_math_rules.
This is the same flag TGSI sets for LEGACY_MATH_RULES.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Tested-by: Mobin Aydinfar <mobin@mobintestserver.ir>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
2022-06-10 03:26:33 +00:00
Timothy Arceri
bc0f8455e5 nouveau/nvc0: disable GLSL IR loop unrolling
NIR loop unrolling is already enabled so just let it do its job.

Shader-db results (nv120):

total gpr in shared programs: 893490 -> 893898 (0.05%)
gpr in affected programs: 15338 -> 15746 (2.66%)
total instructions in shared programs: 6243205 -> 6237068 (-0.10%)
instructions in affected programs: 71160 -> 65023 (-8.62%)
total bytes in shared programs: 66729616 -> 66664760 (-0.10%)
bytes in affected programs: 759328 -> 694472 (-8.54%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16366>
2022-06-04 16:11:49 +00:00
Timothy Arceri
e5181c2e23 nouveau/nv50: disable GLSL IR loop unrolling
NIR loop unrolling is already enabled so just let it do its job.

Shader-db results (nv92):

total gpr in shared programs: 734638 -> 735037 (0.05%)
gpr in affected programs: 11058 -> 11457 (3.61%)
total instructions in shared programs: 6073415 -> 6073398 (<.01%)
instructions in affected programs: 10079 -> 10062 (-0.17%)
total bytes in shared programs: 41837432 -> 41838872 (<.01%)
bytes in affected programs: 252504 -> 253944 (0.57%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16366>
2022-06-04 16:11:49 +00:00
Dave Airlie
e90fe826a2 nouveau/codegen: drop gallium headers from the interface.
I know pipe defines are still used internally, but I'd want
better testing, before starting to remove that.

Acked-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Yusuf Khan<yusisamerican@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16763>
2022-06-03 03:57:18 +00:00
Dave Airlie
1f754b7aae nouveau: move codegen to a common higher level directory.
This allows it to be built independently of the gallium driver.

Acked-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Yusuf Khan<yusisamerican@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16763>
2022-06-03 03:57:18 +00:00
Renamed from src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp (Browse further)