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nv50/ir/nir: avoid 8/16 bit dest regs for OP_MOV

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Instructions like

  mov u16 %r78s 0x00ff (0)

are dropped, since they're not supported by the HW, hence avoid using
8/16 bit destination registers for OP_MOV and use the full width of the
register instead.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Danilo Krummrich <dakr@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18109>
This commit is contained in:
Danilo Krummrich 2022-08-08 11:55:53 +02:00
parent 6e2fda15f1
commit ec60dcd870
1 changed files with 2 additions and 2 deletions
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4
src/nouveau/codegen/nv50_ir_from_nir.cpp
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@ -2509,10 +2509,10 @@ Converter::convert(nir_load_const_instr *insn, uint8_t idx)
val = loadImm(getSSA(4), insn->value[idx].u32);
break;
case 16:
val = loadImm(getSSA(2), insn->value[idx].u16);
val = loadImm(getSSA(4), insn->value[idx].u16);
break;
case 8:
val = loadImm(getSSA(1), insn->value[idx].u8);
val = loadImm(getSSA(4), insn->value[idx].u8);
break;
default:
unreachable("unhandled bit size!\n");