Explicit interpolation just loads raw vertex data as-is and lets the FS do
the interpolation manually.
This adds handling of nir_intrinsic_load_input_vertex, which has 2 different
behaviors: undefined vertex ordering and strict vertex ordering.
- dead IO removed correctly
- constants and uniform expressions are propagated normally
- outputs are deduplicated within their own category (strict and non-strict)
- outputs used by explicit interpolation are never treated as "convergent"
- backward inter-shader code motion is skipped
- compaction has 2 new types of vec4 slots:
- mixed 32-bit and 16-bit explicit strict (sharing the same vec4)
- mixed 32-bit and 16-bit explicit non-strict (sharing the same vec4)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28247>
Compaction only moves directly-indexed slots. This prevents unnecessary
num_slots > 1 from appearing in random slots.
Fixes: c66967b5cb - nir: add nir_opt_varyings, new pass optimizing and compacting varyings
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28431>
Backward inter-shader code motion turns ALU results into outputs,
which led to getting IO with unsupported bit sizes. This prevents
that.
There is a new NIR option flag that indicates 16-bit support.
Fixes: c66967b5cb - nir: add nir_opt_varyings, new pass optimizing and compacting varyings
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28431>
Highlights:
- all shader stages and all input/output types are handled, including
inputs and outputs with multiple vertices
- the optimizations performed are: unused input/output removal, constant
and uniform propagation, output deduplication, inter-shader code motion,
and compaction
- constant and uniform propagation and output deduplication work even
if a shader contains multiple stores of the same output, e.g. in GS
- the same optimizations are also performed between output stores and
output loads (for TCS)
- FS inputs are packed agressively. Only flat, interp FP32, and interp
FP16 can't be in the same vec4. Also, if an output value is
non-divergent within a primitive, the corresponding FS input is
opportunistically promoted to flat.
The big comment at the beginning of nir_opt_varyings.c has a detailed
explanation, which is the same as:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/8841
dEQP and GLCTS have incorrect tests that fail with this, see:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/10361
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26819>
