Commit graph

2556 commits

Author SHA1 Message Date
Marek Olšák
1585a5cc6d nir,amd: add nir_intrinsic_load_debug_log_desc_amd and its use
for shader debugging

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27952>
2024-03-22 21:58:02 +00:00
Marek Olšák
6773595ed0 nir: rename AMD XFB intrinsics to *_gfx11_amd
to indicate it's only for gfx11.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27952>
2024-03-22 21:58:02 +00:00
Samuel Pitoiset
be4a6b946a radv: add a workaround for null IBO on GFX6
Based on PAL.

Fixes dEQP-VK.draw.*nulldescriptor_maintenance_5_maintenance6 on GFX6.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28263>
2024-03-20 16:27:58 +00:00
Konstantin Seurer
a78cbc98cc ac: Improve context roll readability
Add new lines to improve visual separation and color registers:
- red = unchanged
- green = changed

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
2024-03-19 16:08:14 +00:00
Konstantin Seurer
bf15688fa1 ac/parse_ib: Implement annotations
Annotates the IB dump with driver specified strings.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
2024-03-19 16:08:13 +00:00
Konstantin Seurer
0f436e0fe1 ac/parse_ib: Replace the parameter list with ac_ib_parser
It's more code but it should be more readable. This also makes adding
optional arguments easier.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
2024-03-19 16:08:13 +00:00
Konstantin Seurer
2e4d365104 ac: Annotate context rolls
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
2024-03-19 16:08:13 +00:00
Marek Olšák
82aca689c1 ac: use the gfx11 shadowed register tables for gfx11.5
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
2024-03-11 23:36:55 +00:00
Samuel Pitoiset
d12984edb8 ac/nir: fix exporting NGG streamout outputs with implicit PrimId from VS/TES
With RADV, when VS/TES and FS are compiled separately, the PrimitiveId
is exported unconditionally because it's not possible to know if the
FS reads it or not. This happens with fast-link GPL and shader object.

Though, the PrimitiveID should be ignored when it's implicitly exported
because otherwise the stream output LDS offset is incorrect.

This fixes a bunch of failures with transform feedback and Zink/RADV
when shader object is enabled on RDNA3.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27981>
2024-03-11 16:28:32 +00:00
Sathishkumar S
f3ab454f07 ac/gpu_info: query the number of ip instance
query the number of ip instances for VCN and JPEG

v2: use num_queues and remove new variable (Marek)
v3: remove whitespace (Leo)
v4: remove redundant print jpeg_decode (Marek)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27884>
2024-03-04 13:41:56 +00:00
Saleemkhan Jamadar
4ed4058910 radeonsi/vcn: set jpeg reg version for gfx 1151
select appropriate jpeg reg version for gfx 1151

Co-authored-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27811>
2024-03-04 04:43:53 +00:00
Yifan Zhang
8446604dd4 amd: Add code to enable gfx11.5.1
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27811>
2024-03-04 04:43:53 +00:00
David Rosca
cbbed6ca3e radeonsi/vcn: Implement separate QP for I/P/B frames
This also fixes max_au_size as a side effect of using new IB.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27558>
2024-02-29 16:12:13 +00:00
Ruijing Dong
5663221bdb radeonsi/vcn: data structure av1 enc long term reference.
Here it borrowed the term "long term reference" to represent
the customized reference frame rather than the default ones used.

To enable that, it needs application to leverage VAAPI existing
interface to mark a frame as "long term reference", and then
it will be preserved in the DPB for later usage. This preserved
frame later could be refered to by having its signature used in
the ref_frame_idx[] list, and the index can be indicated by
RefFrameCtrl index2, which has not been used for other purpose.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27771>
2024-02-27 20:20:45 +00:00
Konstantin Seurer
d95c30b6ec ac/parese_ib: Handle more packets
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
2024-02-22 19:25:39 +00:00
Konstantin Seurer
ebbbca005e ac/parse_ib: Handle 32bit PKT3_DISPATCH_INDIRECT addrs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
2024-02-22 19:25:39 +00:00
Konstantin Seurer
fea21e5649 ac/parse_ib: Annotate addresses with UAF/OOB info
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
2024-02-22 19:25:39 +00:00
Konstantin Seurer
badd2131b5 ac/parse_ib: Dump the ADDR field of PKT3_SET_BASE
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
2024-02-22 19:25:39 +00:00
Konstantin Seurer
160d18b273 ac/parse_ib: Add and use print_addr
Writes the whole address on one line.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
2024-02-22 19:25:39 +00:00
Konstantin Seurer
ba6d6e5ee1 amd/common: Use the correct register table for GFX10_3
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27322>
2024-02-12 14:04:24 +00:00
Pierre-Eric Pelloux-Prayer
02fe3c32cd ac, radeonsi: remove has_syncobj, has_fence_to_handle
syncobj support is now required so these features are always
available.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24724>
2024-01-26 16:02:26 +00:00
Pierre-Eric Pelloux-Prayer
d25201903d winsys/amdgpu: use syncobj rather than amdgpu fence
syncobjs provide the same features and allow to unify code
paths because we don't need to handle imported syncobj
separately.

This simplifies the code and doesn't seem to have any perf
impact.

Syncobjs are supported in amdgpu since kernel commit 660e855813f78
during 4.12 cycle but the minor version wasn't bumped so use
the next bump value asthe minimum supported version.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24724>
2024-01-26 16:02:26 +00:00
Karol Herbst
f2b7c4ce29 nir: rework and fix rotate lowering
No driver supports urol/uror on all bit sizes. Intel gen11+ only for 16
and 32 bit, Nvidia GV100+ only for 32 bit. Etnaviv can support it on 8,
16 and 32 bit.

Also turn the `lower` into a `has` option as only two drivers actually
support `uror` and `urol` at this momemt.

Fixes crashes with CL integer_rotate on iris and nouveau since we emit
urol for `rotate`.

v2: always lower 64 bit

Fixes: fe0965afa6 ("spirv: Don't use libclc for rotate")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by (Intel and nir): Ian Romanick <ian.d.romanick@intel.com>

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27090>
2024-01-22 10:27:44 +00:00
Samuel Pitoiset
5c03cdbd02 radv: fix indirect dispatches on the compute queue on GFX7
GFX7 CP requires the indirect dispatch VA to be aligned to 32-bytes.

This fixes dEQP-VK.api.command_buffers.many_indirect_disps_on_secondary,
but it's unexpected that it uncovered this bug.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27148>
2024-01-22 07:41:05 +00:00
Marek Olšák
b9b00a0e7a ac,radeonsi: emulate GS primitive pipeline stat on gfx11 because of culling
GS culls too, so the pipeline stat is incorrect. This can be exposed by
forcing monolithic shader use, which makes culling shaders immediately
available for tests to use.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26917>
2024-01-17 09:05:55 +00:00
Marek Olšák
1d3f937142 ac/nir: simplify code at the beginning of ac_nir_gs_shader_query
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26917>
2024-01-17 09:05:54 +00:00
Marek Olšák
4747bd6ba8 ac/nir: optimize out multiplications in small line culling
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26917>
2024-01-17 09:05:54 +00:00
Marek Olšák
0d74123633 ac/nir: rename clipdist_enable_mask -> clip_cull_dist_mask
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26917>
2024-01-17 09:05:54 +00:00
Marek Olšák
af4e91f6b8 ac/nir: don't write TCS outputs to memory if no_varying is set
nir_opt_varyings() will set this, making it unnecessary to look
at the TES input mask.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26917>
2024-01-17 09:05:54 +00:00
Marek Olšák
4880c1e12e amd: unify NIR options between RADV and radeonsi
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26917>
2024-01-17 09:05:54 +00:00
Pierre-Eric Pelloux-Prayer
4e76c4ecb4 radeonsi: compute epitch when modifying surf_pitch
In the linear case with no mipmaps addrlib sets epitch to surf_pitch - 1
so lets do the same thing here.

The change in si_descriptors.c looks like it's papering over a bug but I
couldn't find any other changes that wouldn't break at least one use case.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10375
Fixes: 115b61e51f ("ac/surface: don't oversize surf_size")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26947>
2024-01-12 14:42:55 +00:00
Sergi Blanch Torne
ab6f7170e0 Revert "ac/nir: Export clip distances according to clip_cull_mask"
This reverts commit b38c776690.

This commit seems to offend radeonsi-raven-piglit and radeonsi-stoney-gl.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26941>
2024-01-09 02:36:19 +00:00
Konstantin Seurer
b38c776690 ac/nir: Export clip distances according to clip_cull_mask
Avoids a mismatch between PA_CL_VS_OUT_CNTL and what the shader exports.
Outputs that are not written export zero.

Fixes: f823581 ("ac/nir: add ac_nir_export_position")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9187
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26812>
2024-01-08 08:35:35 +00:00
Vinson Lee
568f61787a ac/rgp: Fix single-bit-bitfield-constant-conversion warning
../src/amd/common/ac_rgp.c:119:48: warning: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Wsingle-bit-bitfield-constant-conversion]
  119 |    header->flags.is_semaphore_queue_timing_etw = 1;
      |                                                ^ ~

Fixes: ed0c852243 ("radv: add initial SQTT files generation support")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26839>
2024-01-05 22:42:58 -08:00
Rhys Perry
ae54cbeb3f nir: remove sad_u8x4
All uses of this can be replaced with msad_4x8.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26907>
2024-01-05 18:55:22 +00:00
Yonggang Luo
19fca131b1 amd: Use align64 instead of ALIGN for 64 bit value parameter
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26869>
2024-01-03 22:02:17 +00:00
Pierre-Eric Pelloux-Prayer
115b61e51f ac/surface: don't oversize surf_size
Yet another iteration on the same YUV surfaces.

The change from 87ecfdfbf0 has 2 odd things:
* it's using MAX2(original value, new value) but the point of updating
  surf_slice_size / surf_size is to make it correct relative to the new
  value of surf_pitch
* it's multiplying surf_pitch (= number of elements per row) by height (ok)
  by surf->bpe (= number of bytes per element) by surf->blk_w (= number of
  "horizontal" pixels in an element) so the end unit doesn't make sense.

Fix this by computing a reasonnable value based on unit: the surf_slice_size
is the number of elements per row (surf_pitch) x number of bytes per element
(bpe) x number of rows.

This makes the expected size correct and thus fixes users of eglCreateImageKHR,
like the issue #6131.

I tested a bunch of gst pipelines and ffmpeg scripts on various files I have
and didn't notice any issues (on gfx10.3 and gfx9).

Fixes: 87ecfdfbf0 ("ac/surface: adapt surf_size when modifying surf_pitch")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6131
Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26693>
2024-01-02 14:32:05 +01:00
Ruijing Dong
434a53ebbe radesonsi/vcn add qp_map definition
This is for enabling ROI (region of interest)
feature in VAAPI interface. It will support
both CQP and rate control mode.

Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26659>
2023-12-15 14:06:34 +00:00
Marek Olšák
390f26eefb ac,radeonsi: require DRM 3.27+ (kernel 4.20+) same as RADV
The only major change is the code removal of the legacy BO list path
in the winsys, which required switching "debug_all_bos" to the new path.

Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26547>
2023-12-13 16:26:17 +00:00
Daniel Schürmann
f5bdc46a57 amd: rename max_wave64_per_simd -> max_waves_per_simd
These are hard limits and don't depend on wave size.
Accordingly, also update the usage in order to avoid
reporting unreasonable occupancy.

Totals from 192 (0.24% of 79330) affected shaders:

MaxWaves: 5814 -> 3072 (-47.16%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26521>
2023-12-11 10:39:50 +00:00
Marek Olšák
2f281b39ab ac/gpu_info: fix printing radeon_info after adding VPE
Fixes: 3ec397819e - amd: add new hardware ip for vpe

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-09 00:05:28 +00:00
Marek Olšák
00dd4d400e ac,radeonsi: rename pos_inputs -> fragcoord_components
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-09 00:05:27 +00:00
Yonggang Luo
72e30c8853 treewide: Avoid use align as variable, replace it with other names
align is a function and when we want use it, the align variable will shadow it
So replace it with other names

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25997>
2023-12-07 02:30:53 +00:00
Samuel Pitoiset
b2a37b4304 ac/nir: add an option to skip MRTZ exports in ac_nir_lower_ps()
On RDNA3, alpha to coverage needs to be exported through MRTZ when
depth, stencil or samplemask are also exported. This option will allow
us to export MRTZ from PS epilogs instead of the main FS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Marek Olšák
7ffb65f935 ac: add an IB parser that gathers context rolls
This is an important performance bottleneck analysis tool.

Try it with radeonsi: AMD_ROLLS=filename app

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
2023-12-01 01:15:55 +00:00
Marek Olšák
f0cb8852a4 ac: move the IB parsers into ac_parse_ib.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
2023-12-01 01:15:55 +00:00
Marek Olšák
c5fe2780e6 ac: rename ac_parse_ib.c -> ac_ib_parser.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
2023-12-01 01:15:55 +00:00
Peyton Lee
3ec397819e amd: add new hardware ip for vpe
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
2023-12-01 00:23:38 +00:00
Rhys Perry
5bc27e80c9 ac/nir: fix 32-bit offset global access optimization
Since 38cff03e58 ("radv: use nir_lower_conv64"), u2u64(a) is replaced
with pack_64_2x32_split(a, 0).

fossil-db (navi31):
Totals from 1203 (1.52% of 79330) affected shaders:
MaxWaves: 33685 -> 33813 (+0.38%)
Instrs: 1407031 -> 1374689 (-2.30%); split: -2.32%, +0.02%
CodeSize: 7088652 -> 6917320 (-2.42%); split: -2.43%, +0.01%
VGPRs: 69276 -> 68988 (-0.42%); split: -0.43%, +0.02%
SpillSGPRs: 982 -> 977 (-0.51%); split: -0.92%, +0.41%
Latency: 12536511 -> 12451605 (-0.68%); split: -0.94%, +0.27%
InvThroughput: 2456803 -> 2431241 (-1.04%); split: -1.09%, +0.05%
VClause: 27624 -> 27832 (+0.75%); split: -1.88%, +2.64%
SClause: 31757 -> 32702 (+2.98%); split: -0.53%, +3.51%
Copies: 90923 -> 91238 (+0.35%); split: -1.47%, +1.81%
Branches: 25127 -> 25128 (+0.00%); split: -0.00%, +0.01%
PreSGPRs: 46025 -> 46068 (+0.09%); split: -0.53%, +0.62%
PreVGPRs: 53944 -> 53488 (-0.85%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
2023-11-30 21:50:21 +00:00
Rhys Perry
10ba06960f ac/nir: ignore 8/16-bit global access offset
This was found by inspection, I'm not sure it can even happen.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
2023-11-30 21:50:21 +00:00