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ac/nir: add ac_nir_export_position
Used by last VGT stage to export position related outputs. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
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Qiang Yu
Marge Bot
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2 changed files with 166 additions and 0 deletions
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@ -56,6 +56,164 @@ ac_nir_export_primitive(nir_builder *b, nir_ssa_def *prim)
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.write_mask = write_mask);
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}
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static nir_ssa_def *
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get_export_output(nir_builder *b, nir_ssa_def **output)
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{
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nir_ssa_def *vec[4];
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for (int i = 0; i < 4; i++) {
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if (output[i])
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vec[i] = nir_u2uN(b, output[i], 32);
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else
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vec[i] = nir_ssa_undef(b, 1, 32);
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}
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return nir_vec(b, vec, 4);
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}
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void
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ac_nir_export_position(nir_builder *b,
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enum amd_gfx_level gfx_level,
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uint32_t clip_cull_mask,
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bool no_param_export,
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uint64_t outputs_written,
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nir_ssa_def *(*outputs)[4])
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{
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nir_intrinsic_instr *exp[4];
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unsigned exp_num = 0;
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nir_ssa_def *pos;
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if (outputs_written & VARYING_BIT_POS) {
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pos = get_export_output(b, outputs[VARYING_SLOT_POS]);
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} else {
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nir_ssa_def *zero = nir_imm_float(b, 0);
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nir_ssa_def *one = nir_imm_float(b, 1);
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pos = nir_vec4(b, zero, zero, zero, one);
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}
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/* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
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* Setting valid_mask=1 prevents it and has no other effect.
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*/
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unsigned pos_flags = gfx_level == GFX10 ? AC_EXP_FLAG_VALID_MASK : 0;
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exp[exp_num] = nir_export_amd(
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b, pos, .base = V_008DFC_SQ_EXP_POS + exp_num,
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.flags = pos_flags, .write_mask = 0xf);
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exp_num++;
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uint64_t mask =
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VARYING_BIT_PSIZ |
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VARYING_BIT_EDGE |
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VARYING_BIT_LAYER |
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VARYING_BIT_VIEWPORT |
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VARYING_BIT_PRIMITIVE_SHADING_RATE;
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/* clear output mask if no one written */
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if (!outputs[VARYING_SLOT_PSIZ][0])
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outputs_written &= ~VARYING_BIT_PSIZ;
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if (!outputs[VARYING_SLOT_EDGE][0])
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outputs_written &= ~VARYING_BIT_EDGE;
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if (!outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE][0])
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outputs_written &= ~VARYING_BIT_PRIMITIVE_SHADING_RATE;
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if (!outputs[VARYING_SLOT_LAYER][0])
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outputs_written &= ~VARYING_BIT_LAYER;
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if (!outputs[VARYING_SLOT_VIEWPORT][0])
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outputs_written &= ~VARYING_BIT_VIEWPORT;
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if (outputs_written & mask) {
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nir_ssa_def *zero = nir_imm_float(b, 0);
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nir_ssa_def *vec[4] = { zero, zero, zero, zero };
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unsigned flags = 0;
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unsigned write_mask = 0;
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if (outputs_written & VARYING_BIT_PSIZ) {
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vec[0] = outputs[VARYING_SLOT_PSIZ][0];
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write_mask |= BITFIELD_BIT(0);
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}
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if (outputs_written & VARYING_BIT_EDGE) {
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vec[1] = nir_umin(b, outputs[VARYING_SLOT_EDGE][0], nir_imm_int(b, 1));
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write_mask |= BITFIELD_BIT(1);
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}
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if (outputs_written & VARYING_BIT_PRIMITIVE_SHADING_RATE) {
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vec[1] = nir_ior(b, vec[1], outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE][0]);
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write_mask |= BITFIELD_BIT(1);
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}
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if (outputs_written & VARYING_BIT_LAYER) {
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vec[2] = outputs[VARYING_SLOT_LAYER][0];
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write_mask |= BITFIELD_BIT(2);
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}
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if (outputs_written & VARYING_BIT_VIEWPORT) {
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if (gfx_level >= GFX9) {
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/* GFX9 has the layer in [10:0] and the viewport index in [19:16]. */
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nir_ssa_def *v = nir_ishl_imm(b, outputs[VARYING_SLOT_VIEWPORT][0], 16);
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vec[2] = nir_ior(b, vec[2], v);
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write_mask |= BITFIELD_BIT(2);
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} else {
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vec[3] = outputs[VARYING_SLOT_VIEWPORT][0];
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write_mask |= BITFIELD_BIT(3);
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}
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}
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exp[exp_num] = nir_export_amd(
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b, nir_vec(b, vec, 4),
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.base = V_008DFC_SQ_EXP_POS + exp_num,
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.flags = flags,
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.write_mask = write_mask);
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exp_num++;
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}
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for (int i = 0; i < 2; i++) {
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if ((outputs_written & (VARYING_BIT_CLIP_DIST0 << i)) &&
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(clip_cull_mask & BITFIELD_RANGE(i * 4, 4))) {
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exp[exp_num] = nir_export_amd(
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b, get_export_output(b, outputs[VARYING_SLOT_CLIP_DIST0 + i]),
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.base = V_008DFC_SQ_EXP_POS + exp_num,
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.write_mask = (clip_cull_mask >> (i * 4)) & 0xf);
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exp_num++;
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}
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}
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if (outputs_written & VARYING_BIT_CLIP_VERTEX) {
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nir_ssa_def *vtx = get_export_output(b, outputs[VARYING_SLOT_CLIP_VERTEX]);
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/* Clip distance for clip vertex to each user clip plane. */
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nir_ssa_def *clip_dist[8] = {0};
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u_foreach_bit (i, clip_cull_mask) {
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nir_ssa_def *ucp = nir_load_user_clip_plane(b, .ucp_id = i);
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clip_dist[i] = nir_fdot4(b, vtx, ucp);
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}
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for (int i = 0; i < 2; i++) {
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if (clip_cull_mask & BITFIELD_RANGE(i * 4, 4)) {
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exp[exp_num] = nir_export_amd(
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b, get_export_output(b, clip_dist + i * 4),
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.base = V_008DFC_SQ_EXP_POS + exp_num,
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.write_mask = (clip_cull_mask >> (i * 4)) & 0xf);
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exp_num++;
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}
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}
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}
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/* Specify that this is the last export */
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nir_intrinsic_instr *final_exp = exp[exp_num - 1];
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unsigned final_exp_flags = nir_intrinsic_flags(final_exp);
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nir_intrinsic_set_flags(final_exp, final_exp_flags | AC_EXP_FLAG_DONE);
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/* If a shader has no param exports, rasterization can start before
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* the shader finishes and thus memory stores might not finish before
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* the pixel shader starts.
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*/
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if (gfx_level >= GFX10 && no_param_export && b->shader->info.writes_memory) {
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nir_intrinsic_instr *wait_instr =
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nir_intrinsic_instr_create(b->shader, nir_intrinsic_memory_barrier_buffer);
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nir_instr_insert_before(&final_exp->instr, &wait_instr->instr);
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}
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}
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/**
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* This function takes an I/O intrinsic like load/store_input,
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* and emits a sequence that calculates the full offset of that instruction,
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@ -76,6 +76,14 @@ ac_nir_unpack_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct a
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void
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ac_nir_export_primitive(nir_builder *b, nir_ssa_def *prim);
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void
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ac_nir_export_position(nir_builder *b,
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enum amd_gfx_level gfx_level,
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uint32_t clip_cull_mask,
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bool no_param_export,
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uint64_t outputs_written,
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nir_ssa_def *(*outputs)[4]);
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nir_ssa_def *
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ac_nir_calc_io_offset(nir_builder *b,
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nir_intrinsic_instr *intrin,
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