Commit graph

157614 commits

Author SHA1 Message Date
Erik Faye-Lund
b9ba2c272a glsl: remove ir_state_slot::swizzle
Same story as with the NIR counterpart in the previous commit.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22620>
2023-04-26 05:51:39 +00:00
Erik Faye-Lund
4e8b532db3 nir: remove nir_state_slot::swizzle
This is only ever written to, never read from. Let's just get rid of it!

This also saves us a few needless includes.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22620>
2023-04-26 05:51:39 +00:00
Mike Blumenkrantz
4c47d83051 zink: use EXT_shader_object to implement generic separate shader precompile
this adds precompile for all separate shader stages (+tcs,tes,geom)
using separate shaders, which should eliminate stuttering for games
using it (e.g., Tomb Raider)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
234f9953a2 zink: fix longstanding TODO for generated tcs
with dynamic pcp this doesn't matter, and this should only be reached
in async mode if dynamic pcp is available

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
d5a3e2db89 zink: handle all stages in fixup_io_locations()
this makes the handling a bit more complex, as both input and output
need to be handled for most stages, and also the per-component handling
gets trickier

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
7a83d6289e zink: move separate shader creation to shader CSO creation
this is a more logical place for it and also enables u_blitter
shaders to be fast-linked

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
0d448d441c zink: use a more standardized loop for initing separate shader program descriptors
this should be identical to previous behavior

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
01694e5bf3 zink: assign separate shader prog stages from ctx->shader_stages
this is functionally equivalent given the checks above which already
restrict which stages can be passed

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
7415627853 zink: move some shader CSO functions around
no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
fe095fcdcd zink: switch to a regular loop to wait on precompile shader fences
even if these aren't done yet, it'll still be faster to wait than
to start compiling new pipelines now

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
ab8499fe00 zink: streamline separate shader descriptor update
no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
991d9d9924 zink: simplify separate shader prog init a little
no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
38d149ffc7 zink: use intermediate variable for separate shader db resize check
no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Mike Blumenkrantz
f46e5f2c0c zink: use intermediate variable for separate shader descriptor update loop
no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22671>
2023-04-26 05:12:25 +00:00
Qiang Yu
5c287290d8 aco,radv: remove unused aco compile options
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
a4b60295a7 aco,ac/llvm,radv,radeonsi: handle ps bc optimization in nir for radv
The side effect is removing the aco/llvm backend bc optimization code
and linear/persp_centroid variable.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
df74919bc2 ac/nir/ps: remove used nir_variable if created
RADV won't do this, so remove them at last.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
bfcf03872e radv: implement nir_load_barycentric_optimize_amd
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
33d683bf09 ac/llvm: remove output variable declaration for radv ps
radv ps does not support epilog when llvm, so outputs will always
be lowered to exports in nir.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
290c3d360e aco,radv: lower outputs to exports when nir for monolithic ps
Remove the compiler backend code for outputs to exports.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
d3611af389 aco: support nir_export_amd with ps targets
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
471418077a ac/nir/ps: add no_color_export option
For radv which always do ps lower but may use epilog or not.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
c877d26454 ac/nir/ps: use nir_export_dual_src_blend_amd when aco
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
9763b6e0da aco: implement nir_export_dual_src_blend_amd
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
583402a332 aco: move create_fs_dual_src_export_gfx11 above
Will be used in visit_intrinsic(), content is not changed.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Qiang Yu
eb1fe8c32f nir: add nir_export_dual_src_blend_amd intrinsic
For GFX11 export dual source blend outputs when ACO.
ACO need a pseudo instruction to emit a block of
code which can't be done in nir currently.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Rhys Perry
01f4addc18 ac/nir/ps: fix null export write mask miss set to 0xf
Fixes: c182154456 ("ac/nir: add ac_nir_lower_ps")
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
Daniel Schürmann
1080ff3971 radv/rt: remove merged VkRayTracingShaderGroupCreateInfoKHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>
2023-04-26 02:48:29 +00:00
Daniel Schürmann
b72c50a885 radv/rt: replace uses of pGroups with radv_ray_tracing_group
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>
2023-04-26 02:48:29 +00:00
Friedrich Vock
c809c05f4f radv: Hash pipeline libraries separately
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>
2023-04-26 02:48:29 +00:00
Daniel Schürmann
a98b44cd34 radv/rt: add shader stage indices to radv_ray_tracing_group
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>
2023-04-26 02:48:29 +00:00
Daniel Schürmann
1a0ae06091 radv/rt: rename radv_ray_tracing_module -> radv_ray_tracing_group
This name better reflects the purpose and content of this struct.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22686>
2023-04-26 02:48:29 +00:00
Charmaine Lee
c661f38342 svga: set PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY for VGPU10 device
Instead of forcing vertex buffer stride to be 4 byte aligned only,
DX10 actually allows the stride to be non 4-byte aligned but the
alignment of an element must be the nearest power of 2 greater or equal to the
width of the element's format, or 4, whichever is less.  So the requirement is
better met with PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY which if set to
TRUE, the sum of vertex element offset + vertex buffer offset + vertex buffer
stride must be aligned to the vertex attributes component size.
Note: PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY cannot be set
with other alignment-requiring CAPs, so we have to return 0 for all the
other alignement CAPs.

This avoids some unnecessary software vertex translate fallback.

cc: mesa-stable

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22689>
2023-04-26 02:29:34 +00:00
Mark Janes
acb2a7d2ec intel/dev: report stepping for TGL systems
Workaround 14010672564 requires a check for the TGL B0 stepping.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>
2023-04-26 02:00:17 +00:00
Mark Janes
47ac056d0f intel/dev: update mesa_defs.json from defect database
These modifications represent:

 * changes to defects made since Feb 16, 2023
 * changes to automated processing of defect state

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>
2023-04-26 02:00:17 +00:00
Illia Polishchuk
45ea17d244 glx: add fail check for current context in another thread
The GLX spec for glXMakeCurrent (3.3):
"If ctx is current to some other thread, then glXMakeCurrent will generate
a BadAccess error"

The GLX spec for glXCopyContext (3.3):
"If the destination context is current for some thread then a BadAccess
error is generated"

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7961
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22546>
2023-04-26 00:20:08 +00:00
Daniel Schürmann
2795cf7422 radv/rt: properly destroy radv_ray_tracing_lib_pipeline on error
Also return the correct error code.

Fixes: 4dafb69d61 ('radv/rt: defer library_pipeline allocation')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22684>
2023-04-25 23:52:49 +00:00
Emma Anholt
74a8f118a2 ci/zink: Try to update TGL results for new MSAA behavior.
A few fixes, but mostly tons of new GPU hangs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22691>
2023-04-25 22:36:15 +00:00
Emma Anholt
0e9036c55e ci/crocus: Note a recent regression.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22691>
2023-04-25 22:36:15 +00:00
Emma Anholt
72520e5a7b ci/lima: Skip ppgtt_memory_alignment that flaked a job with the oomkiller.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22691>
2023-04-25 22:36:15 +00:00
Emma Anholt
35157270c8 ci/panfrost: Drop tex3d-maxsize on g52.
Implicated in 3 job-level flakes where Xorg got killed yesterday.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22691>
2023-04-25 22:36:15 +00:00
David Heidelberg
3f553c6adb ci: add Adreno 660 on sm8350 chipset (HDK 888)
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22604>
2023-04-25 20:41:50 +00:00
Patrick Lerda
6a8e6716ac aux/draw: fix memory leak related to ureg_get_tokens()
Indeed, the function nir_to_tgsi() returns an ureg_get_tokens() allocated
object which is assigned locally. The ureg_get_tokens() allocated object
should be freed.

For instance, this issue is triggered with a llvm enabled lima,
"piglit/bin/gl-1.0-rendermode-feedback -auto -fbo":
Direct leak of 512 byte(s) in 1 object(s) allocated from:
    #0 0x7faeaa4500 in __interceptor_realloc (/usr/lib64/libasan.so.6+0xa4500)
    #1 0x7fa4a88f1c in tokens_expand ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:239
    #2 0x7fa4a88f1c in get_tokens ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:262
    #3 0x7fa4a900f4 in copy_instructions ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:2079
    #4 0x7fa4a900f4 in ureg_finalize ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:2129
    #5 0x7fa4a91dfc in ureg_get_tokens ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:2206
    #6 0x7fa4b20a2c in nir_to_tgsi_options ../src/gallium/auxiliary/nir/nir_to_tgsi.c:4011
    #7 0x7fa4a0c914 in draw_create_vertex_shader ../src/gallium/auxiliary/draw/draw_vs.c:77

Fixes: b5e782f5f4 ("aux/draw: use nir_to_tgsi for draw shader in llvm path")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21924>
2023-04-25 20:04:43 +00:00
Friedrich Vock
b73e2df47a radv: Don't leak the RT prolog binary
Fixes: 063d0c90 ("radv: Combine all the parts together with a main loop for an RT pipeline.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22535>
2023-04-25 19:32:42 +00:00
Friedrich Vock
23c2dbd6ba radv/rt: Plug some memory leaks during shader creation
nir_inline_function actually clones instructions instead of moving them.
Free the shaders explicitly after inserting them instead.

Fixes: 207ce6d658 ("radv: Add helper to inline shaders into the main shader.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22535>
2023-04-25 19:32:42 +00:00
Mike Blumenkrantz
32dddb90ad zink: print the type of shader when dumping
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22692>
2023-04-25 19:04:39 +00:00
M Henning
d49c7b9582 nouveau/codegen: Check nir_dest_num_components
instead of reaching into a union and pulling out garbage when
the dest is a reg

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8863
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22674>
2023-04-25 18:17:41 +00:00
Rob Clark
4a00e79486 freedreno/a6xx: Change a618 tile_align_h back to 32
Commit 60bc7c0e22 ("freedreno: Specify GMEM tile alignment per GPU")
changed the tile_align_h from 32 to 16 (which _should_ be the correct
value).  But this is causing failure in android 9 skqp dstreadshuffle.
(But not, seemingly, with the android 11 version of skia+skqp, which
picks the same tile size.  So this is likely papering something over.)

For now, to unblock things, revert back to the previous tile_align_h.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22683>
2023-04-25 17:41:25 +00:00
Rob Clark
d437e389e0 freedreno: Fix resource tracking vs rebind/invalidate
We can now no longer rely on certain dirty bits to re-trigger draw time
resource tracking.  We need to use the new fd_dirty*_resource() APIs.

Fixes `org.skia.skqp.SkQPRunner#gles_recordopts` on android 9.

Fixes: 0a62a874fc ("freedreno: Re-work dirty-resource tracking")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22683>
2023-04-25 17:41:25 +00:00
Friedrich Vock
7cad28571b radv/rmv: Fix import memory
For some import memory, it is valid to specify zero size.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22532>
2023-04-25 16:07:00 +00:00