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aco,radv: remove unused aco compile options

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Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
This commit is contained in:
Qiang Yu 2023-04-13 12:47:47 +08:00 • committed by Marge Bot
parent a4b60295a7
commit 5c287290d8
3 changed files with 4 additions and 15 deletions
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3
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -11079,7 +11079,8 @@ create_fs_jump_to_epilog(isel_context* ctx)
}
}
Temp continue_pc = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->program->info.ps.epilog.pc));
Temp continue_pc =
convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->program->info.ps.epilog_pc));
aco_ptr<Pseudo_instruction> jump{create_instruction<Pseudo_instruction>(
aco_opcode::p_jump_to_epilog, Format::PSEUDO, 1 + color_exports.size(), 0)};

9
src/amd/compiler/aco_shader_info.h
View file

@ -107,16 +107,10 @@ struct aco_shader_info {
bool as_es;
} tes;
struct {
struct aco_ps_epilog_info epilog;
bool writes_z;
bool writes_stencil;
bool writes_sample_mask;
bool has_epilog;
struct ac_arg epilog_pc;
uint32_t num_interp;
unsigned spi_ps_input;
/* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */
bool alpha_to_coverage_via_mrtz;
} ps;
struct {
uint8_t subgroup_size;
@ -134,7 +128,6 @@ enum aco_compiler_debug_level {
};
struct aco_compiler_options {
bool robust_buffer_access;
bool dump_shader;
bool dump_preoptir;
bool record_ir;

7
src/amd/vulkan/radv_aco_shader_info.h
View file

@ -43,7 +43,6 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
const struct radv_shader_args *radv_args,
const struct radv_pipeline_key *radv_key)
{
radv_aco_convert_ps_epilog_key(&aco_info->ps.epilog, &radv_key->ps.epilog, radv_args);
ASSIGN_FIELD(wave_size);
ASSIGN_FIELD(is_ngg);
ASSIGN_FIELD(has_ngg_culling);
@ -63,9 +62,6 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
ASSIGN_FIELD(gs.vertices_out);
ASSIGN_FIELD(tcs.num_lds_blocks);
ASSIGN_FIELD(tes.as_es);
ASSIGN_FIELD(ps.writes_z);
ASSIGN_FIELD(ps.writes_stencil);
ASSIGN_FIELD(ps.writes_sample_mask);
ASSIGN_FIELD(ps.has_epilog);
ASSIGN_FIELD(ps.num_interp);
ASSIGN_FIELD(ps.spi_ps_input);
@ -74,8 +70,8 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size;
aco_info->is_trap_handler_shader = radv_args->type == RADV_SHADER_TYPE_TRAP_HANDLER;
aco_info->tcs.tess_input_vertices = radv_key->tcs.tess_input_vertices;
aco_info->ps.alpha_to_coverage_via_mrtz = radv_key->ps.alpha_to_coverage_via_mrtz;
aco_info->image_2d_view_of_3d = radv_key->image_2d_view_of_3d;
aco_info->ps.epilog_pc = radv_args->ps_epilog_pc;
}
#define ASSIGN_VS_STATE_FIELD(x) aco_info->state.x = radv->state->x
@ -119,7 +115,6 @@ radv_aco_convert_opts(struct aco_compiler_options *aco_info,
const struct radv_nir_compiler_options *radv,
const struct radv_shader_args *radv_args)
{
ASSIGN_FIELD(robust_buffer_access);
ASSIGN_FIELD(dump_shader);
ASSIGN_FIELD(dump_preoptir);
ASSIGN_FIELD(record_ir);