Commit graph

18 commits

Author SHA1 Message Date
Xavi Zhang
4dd4700612 amdgpu/addrlib: Always returns pixelPitch in original pixels 2017-03-30 14:44:33 +02:00
Roy Zhan
ca88f83222 amdgpu/addrlib: support non-power2 height alignment (for linear surface) 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
fbc9ba7559 amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji
The change also modifies function CiLib::HwlPadDimensions to report
adjusted pitch alignment.
2017-03-30 14:44:33 +02:00
Xavi Zhang
145750efba amdgpu/addrlib: Fix number of //
Find ^/{80,99}$  and replace them to 100 "/"

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
4e2668ecd1 amdgpu/addrlib: Cleanup.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Xavi Zhang
d1ecb70ba3 amdgpu/addrlib: Use namespaces
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Kevin Zhao
8912862a40 amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Frans Gu
acaeae2861 amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWN
This can be used by address lib client to ask address lib to select
tile mode.
2017-03-30 14:44:33 +02:00
Xavi Zhang
90029b958e amdgpu/addrlib: Stylish cleanup.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Xavi Zhang
120a5d0e42 amdgpu/addrlib: fix pixel index calculation of thick micro tiling 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
10f7d1cb03 amdgpu/addrlib: add equation generation
1. Add new surface flags needEquation for client driver use to force
the surface tile setting equation compatible. Override 2D/3D macro
tile mode to PRT_* tile mode if this flag is TRUE and num slice > 1.
2. Add numEquations and pEquationTable in ADDR_CREATE_OUTPUT structure
to return number of equations and the equation table to client driver
3. Add equationIndex in ADDR_COMPUTE_SURFACE_INFO_OUTPUT structure to
return the equation index to client driver

Please note the use of address equation has following restrictions:
1) The surface can't be splitable
2) The surface can't have non zero tile swizzle value
3) Surface with > 1 slices must have PRT tile mode, which disable
slice rotation
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
3e44337bd6 amdgpu/addrlib: rename ComputeSurfaceThickness to Thickness 2017-03-30 14:44:33 +02:00
Frans Gu
7293a020bd amdgpu/addrlib: Add new interface to support macro mode index query 2017-03-30 14:44:33 +02:00
XiaoYuan Zheng
6164f23a91 amdgpu/addrlib: add tcCompatible htile addr from coordinate support. 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
8b110f0319 amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex and AddrConvertTileInfoToHW
When clients queries tile Info from tile index and expects accurate
tileSplit info,  bits per pixel info is required to be provided since
this is necessary for computing tileSplitBytes; otherwise Addrlib will
return value of "tileBytes" instead if bpp is 0 - which is also
current logic. If clients don't need tileSplit info, it's OK to pass
bpp with value 0.
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
e06aeaf19f amdgpu/addrlib: style changes and minor cleanups
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
cb5d22a3f3 amdgpu/addrlib: AddrLib inheritance refactor
Add one more abstraction layer into inheritance system.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
52a1288a15 amdgpu/addrlib: rearrange code in preparation of refactoring
No code changes.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00