We can't move discards across side effects, or the side effect might not happen.
Fixes KHR-GLES31.core.shader_image_load_store.basic-allFormats-load-fs
regression. Sigh.
CI is up next.
Fixes: 119e5b9719 ("agx: Schedule for register pressure")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26056>
nir_index_ssa_defs(..) will re-index the function impl and will
update ssa_alloc. In almost all cases this will result in a lower
ctx->alloc number which reduces memory usage in compiler passes
that are using ctx-alloc to allocate memory.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26056>
Adapt gen_pack.py to generate an OpenCL compatible header, capable of both
packing and unpacking but not printing (due to no known use case and no fprintf
in CL). This is useful as a building block for manipulating descriptors from
shader code, for example in texture lowering or device-generated commands.
To accomplish this, we need to inline in some CL-compatible variants of mesa
util functions (no doubles, etc), avoid FILE * use in the CL path, and use
__constant pointers where applicable for performance. Otherwise, there are
surprisingly few changes required, thanks mainly to CL 2.0 generic pointers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25498>
The loop is supposed to execute exactly once, but the previous logic
inadvertently executes 0 or 1 times depending on whether dst is NULL (it never
is). Reexpress the loop to execute exactly once, eliminating the unnecessary
branch in this hot path. Noticed when reading the NIR of generated pack code.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25498>
This will clean up genxml unpack code and is needed for parity with the assembly
we write by hand. This way we get the win for all shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25498>
for buffer textures, we insert new blocks which invalidates dominance and
block index info... leads to end-to-end fails when shuffling pass order.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25498>
First, we need to give the parent_instr field a unique name to be able to
replace with a helper. We have parent_instr fields for both nir_src and
nir_def, so let's rename nir_src::parent_instr in preparation for rework.
This was done with a combination of sed and manual fix-ups.
Then we use semantic patches plus manual fixups:
@@
expression s;
@@
-s->renamed_parent_instr
+nir_src_parent_instr(s)
@@
expression s;
@@
-s.renamed_parent_instr
+nir_src_parent_instr(&s)
@@
expression s;
@@
-s->parent_if
+nir_src_parent_if(s)
@@
expression s;
@@
-s.renamed_parent_if
+nir_src_parent_if(&s)
@@
expression s;
@@
-s->is_if
+nir_src_is_if(s)
@@
expression s;
@@
-s.is_if
+nir_src_is_if(&s)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
If we spill render targets with a layered framebuffer, our spilled targets are
assumed to be 2D Arrays (in general). We need to use arrayed image operations to
load/store from these. The layer is given by the layer as read in the fragemnt
shader. This handles the eMRT portion of layered rendering.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Just add a flag for it. We don't care about the actual # of layers when
calculating the layout, only the boolean fact of being layered or not. The
reason we need this at all is because the eMRT implementation needs to
account for layering and that is only keyed off the tilebuffer layout.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
The hardware needs the layer ID and the viewport index packed together. That
consumes an entire varying slot, if we want those available in the frag shader
we need a separate slot. Add a pass to insert the extra packed write.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
With the exception of the backwards branch for loops, all the control flow we
insert during instruction selection just predicates instructions rather than
actually jumping around. That means, for example, we execute both sides of the
if even for a uniform condition! That's inefficient. The solution is insert
jmp_exec_none instructions after control flow in order to skip unexecuted
regions, which is much faster than predicating them out. However, jmp_exec_none
is costly in itself, so we need to use a heuristic to determine when it's
actually beneficial.
This uses a very simple heuristic for this purpose. However, it is a massive
performance speed-up for Dolphin uber shaders: 39fps -> 67fps at 2x resolution.
Nearly a doubling of performance!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
jmp_exec_none variant that jumps to the last instruction of the target block,
rather than the beginning. This is convenient for skipping over elses, while
still executing the block-final pop_exec instruction. Similarly for skipping
over loop bodies while still executing the block-final pop_exec, after break
instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Add an optional pointer to a target block for these instructions. This does NOT
act like a logical branch, and does NOT get added to the logical control flow.
It is ignored wholesale until after RA, when physical edges may be inserted by a
pass we add later in this series.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Although this is well-motivated, perf effect seems to be neglible for Dolphin.
It does prevent the scheduler from making things worse by sinking these
instructions though, so as a way to prevent future problems this seems sensible.
The kind of problem this affects (late discard) isn't modelled in shader-db.
Nevertheless, nothing concerning there:
total instructions in shared programs: 1756699 -> 1756722 (<.01%)
instructions in affected programs: 10106 -> 10129 (0.23%)
helped: 21
HURT: 41
Inconclusive result (value mean confidence interval includes 0).
total bytes in shared programs: 11525404 -> 11525452 (<.01%)
bytes in affected programs: 72900 -> 72948 (0.07%)
helped: 27
HURT: 41
Inconclusive result (value mean confidence interval includes 0).
total halfregs in shared programs: 483394 -> 483286 (-0.02%)
halfregs in affected programs: 4945 -> 4837 (-2.18%)
helped: 88
HURT: 78
Inconclusive result (value mean confidence interval includes 0).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This fixes live range splitting with 3D textureGrad(), which involves vectors
larger than the natural 128-bit maximum and hence requires special handling.
Fixes this assert with a combination of debug flags and new patches:
unsigned int find_best_region_to_evict(struct ra_ctx *, unsigned int,
unsigned int *, unsigned int *):
Assertion `(rctx->bound % size) == 0 && "register file size must be aligned
to the maximum vector size"' failed
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
