All vulkan drivers have been copying anv's code to convert
VkSpecializationInfo into nir_spirv_specialization.
Recently there was a Vulkan spec change on allowed values for
VkSpecializationInfo, and all drivers got affected.
This commits creates a new helper, and uses it on all Vulkan Mesa
drivers.
v2: use (uint8_t*) castings, instead of void*, to avoid C2036 with
MSVC (detected by the CI, inspired on what radv was doing)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12047>
Now we have all our Bifrost unit tests under meson and can remove the
test entrypoint from bifrost_compiler. This does require a small
refactoring for our util_dynarray handling to make sure we don't leak
memory. Otherwise meson-arm64-asan complains.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12109>
This handles the following from the Valhall specification (that I wrote):
If multiple subsequent staging registers are accessed, the base must
be aligned to 2. However, even if 4 registers are accessed, it is
not necessary to align to 4, only to 2. This restriction allows the
hardware to use a 64-bit data path without handling unaligned
access, which is more efficient. This restriction does not apply if
only a single register is accessed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12026>
Decides when we need "branch reconvergence" (canonical term), the
logical opposite of "back-to-back execution" (non-canonical term, this
is old code in Bifrost terms). So invert the return value, rename, and
export so we can use it when packing Valhall instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12026>
Needed to correctly lower sources to moves, used in the FAU lowering.
Technically, the issue is already present on Bifrost, but it's hidden
because Bifrost packing doesn't validate the absense of unsupported
modifiers. Valhall packing adds more safety, which caught this issue.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12026>
Uses the same set of cases. This is a standalone C program because the
easy way of hooking into the disassembler from Python with subprocesses
was slow. This seems cleaner anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
These are lines of assembly that look valid but are not, and should
raise a parser error but not otherwise crash the assembler or produce
invalid code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
These are valid pairs of hexdumped assembled instructions and the
corresponding disassembly, to be used to regression test both the
assembler and the disassembler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
When we bring up the Valhall compiler in Mesa, we will like to have a
disassembler in native code, so we shouldn't write our disassembler in
Python. Instead, we write a disassembler generator in Python with mako
templates, which will produce a va_disasm_instr entrypoint from the
architecture defined in ISA.xml and valhall.py.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
Logic described in the "Uniform/constant restrictions" section of the
Valhall specification. (You know, my Valhall specification. Is there
another one?)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
This Python script acts as a standalone assembler. It takes Valhall
instructions with Mesa-flavour syntax, parses them, errors out if there
are syntax errors, and writes out an assembled binary if there are not.
It also is available as a programmatic interface for automated testing.
While this attempts to handle syntax errors, it does not check
semantics. It will happily compile programs that fault, provided each
instruction locally 'looks' plausible.
The code itself is quite small, despite supporting most of the known
ISA, because the syntax is regular and the heavylifting is done by
ISA.xml and valhall.py.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
