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pan/bi: Rename CLPER_V7 back to CLPER

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v6 is really the oddball here. CLPER on v9 supports a superset of v7.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12026>
This commit is contained in:
Alyssa Rosenzweig 2021-07-23 12:52:57 -04:00 • committed by Marge Bot
parent f9616b7463
commit a5727909e1
5 changed files with 6 additions and 6 deletions
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2
src/panfrost/bifrost/ISA.xml
View file

@ -3694,7 +3694,7 @@
<src start="3"/>
</ins>
<ins name="+CLPER_V7.i32" mask="0xfc000" exact="0x7c000">
<ins name="+CLPER.i32" mask="0xfc000" exact="0x7c000">
<src start="0" mask="0x7"/>
<src start="3"/>
<mod name="lane_op" start="6" size="2">

2
src/panfrost/bifrost/bi_helper_invocations.c
View file

@ -94,8 +94,8 @@ bi_instr_uses_helpers(bi_instr *I)
case BI_OPCODE_VAR_TEX_F16:
case BI_OPCODE_VAR_TEX_F32:
return !I->lod_mode; /* set for zero, clear for computed */
case BI_OPCODE_CLPER_I32:
case BI_OPCODE_CLPER_V6_I32:
case BI_OPCODE_CLPER_V7_I32:
/* Fragment shaders require helpers to implement derivatives.
* Other shader stages don't have helpers at all */
return true;

2
src/panfrost/bifrost/bi_lower_swizzle.c
View file

@ -44,8 +44,8 @@ bi_lower_swizzle_16(bi_context *ctx, bi_instr *ins, unsigned src)
/* Despite ostensibly being 32-bit instructions, CLPER does not
* inherently interpret the data, so it can be used for v2f16
* derivatives, which might require swizzle lowering */
case BI_OPCODE_CLPER_I32:
case BI_OPCODE_CLPER_V6_I32:
case BI_OPCODE_CLPER_V7_I32:
break;
case BI_OPCODE_IADD_V2S16:

2
src/panfrost/bifrost/bi_schedule.c
View file

@ -614,8 +614,8 @@ bi_reads_temps(bi_instr *ins, unsigned src)
{
switch (ins->op) {
/* Cannot permute a temporary */
case BI_OPCODE_CLPER_I32:
case BI_OPCODE_CLPER_V6_I32:
case BI_OPCODE_CLPER_V7_I32:
return src != 0;
case BI_OPCODE_IMULD:
return false;

4
src/panfrost/bifrost/bifrost_compile.c
View file

@ -1971,11 +1971,11 @@ bi_emit_alu(bi_builder *b, nir_alu_instr *instr)
left = bi_clper_v6_i32(b, s0, lane1);
right = bi_clper_v6_i32(b, s0, lane2);
} else {
left = bi_clper_v7_i32(b, s0, lane1,
left = bi_clper_i32(b, s0, lane1,
BI_INACTIVE_RESULT_ZERO, BI_LANE_OP_NONE,
BI_SUBGROUP_SUBGROUP4);
right = bi_clper_v7_i32(b, s0, lane2,
right = bi_clper_i32(b, s0, lane2,
BI_INACTIVE_RESULT_ZERO, BI_LANE_OP_NONE,
BI_SUBGROUP_SUBGROUP4);
}