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Author SHA1 Message Date
Samuel Pitoiset
45c0ef3bb4 radv: dump SPIR-V and NIR for the faulty shader detected with the trap 
More logs is always better for debugging.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32116>
 2024-11-14 15:57:07 +00:00
Samuel Pitoiset
9149488a9d radv: mark live invocations when dumping VGPRS with the trap handler 
Similar to UMR.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32116>
 2024-11-14 15:57:07 +00:00
David Rosca
dcfc956521 radv/video: Override pic_init_qp_minus26 in PPS 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
 2024-11-14 07:52:56 +00:00
David Rosca
d166bb5dd1 radv/video: Use 64x16 alignment for HEVC encode 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
 2024-11-14 07:52:56 +00:00
David Rosca
d1c1a33b35 radv/video: Avoid selecting rc layer over maximum 
Vulkan spec doesn't say if this is allowed or not, but trying
to do this will hang.

Fixes: 4a19047d32 ("radv/video: Select temporal layer when encoding each frame")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
 2024-11-14 07:52:56 +00:00
David Rosca
e941acfb9d radv/video: Report correct encodeInputPictureGranularity 
Only aligned size can be encoded.

Fixes: 54d499818c ("radv/video: add initial support for encoding with h264.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
 2024-11-14 07:52:56 +00:00
David Rosca
e4ec135d8b radv/video: Fix HEVC slice control 
This needs to use aligned size, otherwise it will output two
slices when the size is not 64 aligned.

Fixes: 967e4e09de ("radv/video: add h265 encode support")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
 2024-11-14 07:52:56 +00:00
David Rosca
6a121f1507 radv/video: Fix H264 slice control 
This needs to use aligned size, otherwise it will output two
slices when the size is not 16 aligned.

Fixes: 54d499818c ("radv/video: add initial support for encoding with h264.")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
 2024-11-14 07:52:56 +00:00
Samuel Pitoiset
b4b5f9eeb0 radv,aco: dump VGPRS from the trap handler shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32090>
 2024-11-13 15:27:54 +00:00
Rhys Perry
7d4cc04156 radv,ac/nir: split global access using nir_lower_mem_access_bit_sizes 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
8fdc5d7f9f radv,ac/nir: lower sub-dword loads using nir_lower_mem_access_bit_sizes 
fossil-db (navi21):
Totals from 427 (0.54% of 79395) affected shaders:
Instrs: 2939637 -> 2937224 (-0.08%); split: -0.08%, +0.00%
CodeSize: 15982272 -> 15969880 (-0.08%); split: -0.08%, +0.00%
Latency: 21128645 -> 21125738 (-0.01%); split: -0.04%, +0.03%
InvThroughput: 5626811 -> 5626220 (-0.01%); split: -0.03%, +0.02%
SClause: 65771 -> 65731 (-0.06%); split: -0.07%, +0.00%
Copies: 243247 -> 242917 (-0.14%); split: -0.14%, +0.01%
Branches: 100089 -> 100085 (-0.00%)
PreSGPRs: 17879 -> 18118 (+1.34%)
VALU: 1899641 -> 1899278 (-0.02%)
SALU: 468508 -> 466469 (-0.44%)
SMEM: 84305 -> 84291 (-0.02%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Samuel Pitoiset
44fa24580f radv: optimize the pipe misaligned L2 cache invalidation on GFX11 
When using the subresource range, it's possible to reduce the number
of L2 cache invalidations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
 2024-11-12 17:27:39 +00:00
Samuel Pitoiset
7a3a65c0c4 radv: pass the image subresource range to radv_{src,dst}_access_flush() 
This will allow us to optimize the pipe misaligned special case for
GFX11 because only the first mip in the mip-tail needs the L2 cache
invalidation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
 2024-11-12 17:27:39 +00:00
Samuel Pitoiset
f7a39fac10 radv: use vk_image_view_subresource_range() when possible 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
 2024-11-12 17:27:39 +00:00
Samuel Pitoiset
7a8b725d03 radv: determine the first mip that is pipe misaligned on GFX10+ 
This will allow us to optimize the GFX11 case where not all mips are
affected by the L2 invalidation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
 2024-11-12 17:27:39 +00:00
Samuel Pitoiset
c5d5f2fbef radv: move the GFX11 special case for mips to radv_image_is_pipe_misaligned() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
 2024-11-12 17:27:39 +00:00
Samuel Pitoiset
65bb39bf96 radv: do not always invalidate L2 for GPUs with non-coherent RBs on GFX10+ 
According to PAL, L2 should be invalidated only for images with
DCC/HTILE even on GPUs with non-coherent RBs. In practice, most of
the images have either DCC/HTILE but this can reduce the number of L2
flushes for images without any compression.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
 2024-11-12 17:27:39 +00:00
Samuel Pitoiset
5e0b81413d radv: emit nir_debug_break instructions when the trap handler is enabled 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32061>
 2024-11-12 16:05:17 +00:00
Samuel Pitoiset
5f79b8ea2d radv,aco: save/restore overwritten VGPRs in the trap handler shader 
The trap currently doesn't return to the shader but it will be needed
for example for the debug mode.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
ccde8ecd64 radv: compute the TMA BO size instead of using a constant 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
3e88f996a5 radv: fix the TMA descriptor size 
The TMA BO contains the descriptor first.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
6ec0c85908 radv,aco: use the trap handler layout struct while compiling the shader 
It's less error prone to rely on the layout for offsets.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
6bfd92123f aco: simplify postprocessing the trap handler shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
44dfeb4479 radv,aco: add a separate function to compile the trap handler shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
62e335c779 radv,aco: dump more SQ_WAVE regs from the trap handler 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
0cc21d0601 radv: cleanup printing SGPRS dumped from the trap handler 
It's more readable like that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Georg Lehmann
ece1ab3b87 radv: run copy prop before vectorizing 
Otherwise there are a lot of scalar movs between texture instructions
and alu. With those removed, the top down vectorizer has more starting
points.

Totals from 296 (0.37% of 79206) affected shaders:
MaxWaves: 5710 -> 5754 (+0.77%)
Instrs: 388051 -> 386630 (-0.37%); split: -0.46%, +0.09%
CodeSize: 2120800 -> 2117144 (-0.17%); split: -0.30%, +0.13%
VGPRs: 17496 -> 17344 (-0.87%)
Latency: 8893751 -> 8901364 (+0.09%); split: -0.10%, +0.18%
InvThroughput: 1740411 -> 1731710 (-0.50%); split: -0.57%, +0.07%
VClause: 6573 -> 6576 (+0.05%); split: -0.21%, +0.26%
SClause: 11233 -> 11209 (-0.21%); split: -0.28%, +0.07%
Copies: 31582 -> 31635 (+0.17%); split: -1.49%, +1.66%
PreSGPRs: 15878 -> 15876 (-0.01%)
PreVGPRs: 15380 -> 15274 (-0.69%)
VALU: 278528 -> 277036 (-0.54%); split: -0.65%, +0.11%
SALU: 49062 -> 49054 (-0.02%); split: -0.03%, +0.02%

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32060>
 2024-11-11 18:33:48 +00:00
Samuel Pitoiset
30d9166d80 radv: dump the trap handler shader with RADV_DEBUG=dump_trap_handler 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32031>
 2024-11-11 09:34:05 +00:00
Samuel Pitoiset
4d50691ae9 radv: remove unused parameter to radv_fill_nir_compiler_options() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32031>
 2024-11-11 09:34:05 +00:00
Konstantin Seurer
e3cf6290e0 radv: Add RADV_DEBUG=nirdebuginfo 
Annotates the shader with source locations into the nir shader.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29298>
 2024-11-11 08:39:14 +00:00
Konstantin Seurer
736c8c6f23 radv: Dump nir shaders before compiling 
It will allow adding source locations that point to the nir_string to
the shader.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29298>
 2024-11-11 08:39:14 +00:00
Konstantin Seurer
aaf65d6219 radv: Store debug info inside radv_shader 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29298>
 2024-11-11 08:39:14 +00:00
Konstantin Seurer
54c22656b8 radv: Add a helper for accessing the shader binary 
Use pointers into the blob instead of hardcoding the layout everywhere.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29298>
 2024-11-11 08:39:13 +00:00
Konstantin Seurer
69ebba82d4 aco: Pass debug information to the driver 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29298>
 2024-11-11 08:39:13 +00:00
Konstantin Seurer
c5e40a60f8 radv: Lower non-uniform access after vectorization 
Scalar access can make nir_lower_non_uniform_access emit a lot of
waterfall loops.

Totals from 83 (0.10% of 84770) affected shaders:
Instrs: 2747926 -> 2745959 (-0.07%); split: -0.07%, +0.00%
CodeSize: 15022460 -> 14998240 (-0.16%); split: -0.16%, +0.00%
Latency: 18602932 -> 18404976 (-1.06%); split: -1.18%, +0.12%
InvThroughput: 4500730 -> 4450364 (-1.12%); split: -1.18%, +0.06%
VClause: 93651 -> 91848 (-1.93%); split: -1.93%, +0.00%
SClause: 63672 -> 63595 (-0.12%); split: -0.13%, +0.00%
Copies: 229377 -> 229896 (+0.23%); split: -0.04%, +0.27%
Branches: 107630 -> 107627 (-0.00%); split: -0.01%, +0.00%
PreSGPRs: 5247 -> 5253 (+0.11%)
PreVGPRs: 5911 -> 5903 (-0.14%); split: -0.29%, +0.15%
VALU: 1761158 -> 1761540 (+0.02%); split: -0.01%, +0.03%
SALU: 419743 -> 419783 (+0.01%); split: -0.01%, +0.02%
VMEM: 152142 -> 150208 (-1.27%)
SMEM: 80251 -> 80244 (-0.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30509>
 2024-11-11 07:53:13 +00:00
Samuel Pitoiset
437bd63265 radv,aco: dump m0 and exec from the trap handler 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32026>
 2024-11-08 14:00:15 +00:00
Pierre-Eric Pelloux-Prayer
acc32cadf5 radv: set info->family_overridden when RADV_FORCE_FAMILY is used 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31841>
 2024-11-08 13:31:02 +00:00
Samuel Pitoiset
9cc07bbd09 radv: mark some GFX6-7 GPUs as Vulkan 1.3 conformant 
It's the first time RADV is Vulkan conformant on GFX6-7! Some chips
are missing because we don't have access but most of the GFX6-7 GPUs
are covered.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32022>
 2024-11-07 11:50:10 +00:00
Samuel Pitoiset
b67218645d radv: save the trap handler report in the HOME directory 
It's similar to where GPU hang reports are saved.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31988>
 2024-11-07 09:28:16 +01:00
Georg Lehmann
2cd8a9fef7 amd: lower gl_FragCoord.w rcp in NIR 
This allows NIR to remove the rcps if the application uses rcp(gl_FragCoord.w).
D3D provides w, not 1/w like GL/VK in the shader, so this is commonly used.

Foz-DB Navi21:
Totals from 2068 (2.61% of 79206) affected shaders:
MaxWaves: 45636 -> 45652 (+0.04%)
Instrs: 2173444 -> 2169671 (-0.17%); split: -0.18%, +0.00%
CodeSize: 11881304 -> 11867208 (-0.12%); split: -0.12%, +0.01%
VGPRs: 118000 -> 117968 (-0.03%)
Latency: 35689676 -> 35675909 (-0.04%); split: -0.06%, +0.02%
InvThroughput: 9167199 -> 9159801 (-0.08%); split: -0.08%, +0.00%
VClause: 45076 -> 45078 (+0.00%); split: -0.01%, +0.02%
SClause: 92503 -> 92366 (-0.15%); split: -0.31%, +0.17%
Copies: 140282 -> 140303 (+0.01%); split: -0.13%, +0.14%
Branches: 53347 -> 53346 (-0.00%); split: -0.01%, +0.00%
PreVGPRs: 96495 -> 96465 (-0.03%)
VALU: 1522980 -> 1519252 (-0.24%); split: -0.25%, +0.01%
SALU: 213451 -> 213460 (+0.00%); split: -0.02%, +0.02%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31967>
 2024-11-06 12:57:08 +00:00
Timur Kristóf
766617e8da radv: Enable NGG culling by default on GFX10. 
We never took the time to actually test this, but it works fine.
Improves performance on Navi 10 in the following test cases:

Baldur's Gate 3 Vulkan: up to 10%
Witcher 3 D3D11: around 4%
Granite primitive stress test: 107%
FSR2 sample app: 57%

Notes:
NGG is still disabled on Navi 14.
Not tested on Navi 12.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31971>
 2024-11-06 03:16:54 +00:00
Timur Kristóf
6bf19b2d70 radv: Increase NGG culling PS param limit to 12 on GFX10. 
Helps performance in Baldur's Gate 3 on Navi 10
when NGG culling is enabled.

Also fix the description of the RADV_PERFTEST=nggc env var.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31971>
 2024-11-06 03:16:53 +00:00
Samuel Pitoiset
64774f9c19 radv: cleanup tools related resources when destroying logical device 
This was missing.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31986>
 2024-11-05 15:31:00 +00:00
Samuel Pitoiset
81f4670ed6 radv,aco: dump all SGPRS from the trap handler 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31960>
 2024-11-05 07:58:38 +00:00
Samuel Pitoiset
45d56d9395 radv: set missing shader info values for the trap handler 
This fixes an assert in radv_precompute_registers_pgm() on GFX11
because it was considered a vertex shader.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31962>
 2024-11-05 07:11:30 +00:00
Marek Olšák
755fb7a262 amd: move Tonga and Iceland TC-compat HTILE workarounds to ac_gpu_info.c 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31910>
 2024-11-04 19:45:54 +00:00
Georg Lehmann
a7f6294f90 radv: use nir_opt_frag_coord_to_pixel_coord 
Foz-DB Navi21:
Totals from 1648 (2.08% of 79395) affected shaders:
MaxWaves: 44918 -> 44950 (+0.07%); split: +0.09%, -0.02%
Instrs: 1004193 -> 1001179 (-0.30%); split: -0.33%, +0.03%
CodeSize: 5486412 -> 5486592 (+0.00%); split: -0.08%, +0.09%
VGPRs: 56664 -> 56552 (-0.20%); split: -0.93%, +0.73%
Latency: 15430894 -> 15435320 (+0.03%); split: -0.12%, +0.15%
InvThroughput: 3097789 -> 3092861 (-0.16%); split: -0.20%, +0.04%
VClause: 18757 -> 18793 (+0.19%); split: -0.13%, +0.32%
SClause: 34475 -> 34495 (+0.06%); split: -0.11%, +0.17%
Copies: 66195 -> 66150 (-0.07%); split: -0.88%, +0.81%
Branches: 23035 -> 23033 (-0.01%)
PreVGPRs: 42235 -> 41724 (-1.21%); split: -1.32%, +0.11%
VALU: 709730 -> 706662 (-0.43%); split: -0.47%, +0.04%
SALU: 111731 -> 111722 (-0.01%); split: -0.02%, +0.01%
VMEM: 25988 -> 25987 (-0.00%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31864>
 2024-11-04 12:34:31 +00:00
Georg Lehmann
a2a9e93e72 radv: add support for load_pixel_coord 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31864>
 2024-11-04 12:34:30 +00:00
Samuel Pitoiset
f7636b611a radv: add a struct that describes the trap handler layout 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31934>
 2024-11-01 15:40:25 +00:00
Samuel Pitoiset
49682fc0cb radv,aco: save SQ_WAVE_GPR_ALLOC from the trap handler 
This would be used to dump SGPRs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31934>
 2024-11-01 15:40:25 +00:00