20134 commits

Author	SHA1	Message	Date
Marek Olšák	edd2fc3c7f	radeonsi: use AC_EXP_PARAM_UNDEFINED for clarity ... The code was slightly confusing. Reviewed-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35392>	2025-06-10 03:31:20 +00:00
Marek Olšák	447d744833	ac/llvm: allocate LLVM PS output variables on demand ... This stops relying on si_shader_info, allowing further cleanup of si_shader_info. radv_load_output was unused. Reviewed-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35392>	2025-06-10 03:31:20 +00:00
Dave Airlie	b8ac2d47e7	radv/video: add KHR_video_decode_vp9 support. ... This adds the VP9 decoding support. This was initially developed by me, Stéphane Cerveau from Igalia did a bunch of fixes and testing, Benjamin Cheng from AMD also helped with a few fixes and how to program the firmware better. This passes the current VK-GL-CTS tests. Reviewed-by: David Rosca <david.rosca@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35398>	2025-06-09 20:46:04 +00:00
Dave Airlie	4399e43ffd	ac/vcn: add new firmware flag to pass uncompresed header offset. ... Reviewed-by: David Rosca <david.rosca@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35398>	2025-06-09 20:46:04 +00:00
Dave Airlie	a0f4cbe6f7	amd: move vp9 probs table to common code. ... This will be reused by radv eventually, so let's move it all over to common code. It might have other users eventually, but we can worry about that later. Reviewed-by: David Rosca <david.rosca@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35398>	2025-06-09 20:46:03 +00:00
Natalie Vock	a28515f096	aco/opt: Rename loop header phis ... Fossil stats on top of !35269: Totals from 133 (0.16% of 81077) affected shaders: Instrs: 4328456 -> 4327891 (-0.01%) CodeSize: 22890004 -> 22887732 (-0.01%); split: -0.01%, +0.00% Latency: 28406452 -> 28404732 (-0.01%) InvThroughput: 5361458 -> 5361153 (-0.01%) Copies: 376788 -> 376222 (-0.15%) VALU: 2429210 -> 2428645 (-0.02%) VOPD: 57 -> 56 (-1.75%) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35270>	2025-06-09 14:36:44 +00:00
Rhys Perry	00dd0d0dd1	aco: update VALUReadSGPRHazard comment ... Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35387>	2025-06-09 10:12:25 +00:00
Rhys Perry	a714a19e16	aco/gfx12: fix VALUReadSGPRHazard with carry-out ... fossil-db (gfx1201): Totals from 370 (0.46% of 79653) affected shaders: Instrs: 3933639 -> 3935914 (+0.06%) CodeSize: 20743448 -> 20752068 (+0.04%); split: -0.00%, +0.04% Latency: 26261246 -> 26261921 (+0.00%); split: -0.00%, +0.00% InvThroughput: 5363675 -> 5363760 (+0.00%); split: -0.00%, +0.00% Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Fixes: 65f95ae74e ("aco/insert_NOPs: implement VALU -> VALU case for VALUReadSGPRHazard on GFX12") Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35387>	2025-06-09 10:12:25 +00:00
Marek Olšák	d279d019d4	ac/nir/tess: remove parameter from and simplify hs_per_patch_output_vmem_offset ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	5734a916d6	ac: move tcs_offchip_layout into ac_shader_args ... It's the same variable between radv and radeonsi, but the implementation of the load intrinsics is very different. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	5994e08f8b	ac: set LDS limit for TCS to 32K for all chips ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	fa5e07d5f7	ac/nir/tess: write TCS patch outputs to memory as vec4 stores at the end ... This moves per-patch output VMEM stores to the end of the shader where they execute only once. They are skipped if the whole workgroup discards all patches. If tcs_vertices_out == 1, per-patch output VMEM stores use the same lanes as per-vertex output VMEM stores, which are aligned to 4 or 8 lanes to get cached bandwidth for the stores. Previously, per-patch outputs were stored to memory for every store_output intrinsic in TCS. Additionally, LDS is no longer allocated for per-patch outputs that are only written and read by invocation 0, or they are written by all invocations but not read, and don't have indirect indexing. This reduces LDS usage and LDS traffic. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	c732306c5a	ac/nir/tess: unify computing LDS output patch size, minimize LDS bank conflicts ... This unifies the duplicated LDS output patch size computation between hs_output_lds_offset and ac_nir_compute_tess_wg_info. "+ 4" to the output patch stride minimizes LDS bank conflicts by making the beginning of each patch start on a different LDS bank. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	37dc376395	ac/nir/tess: use if-ladder to determine valid tess level components for the vote ... Checking whether every compoment is valid in tess_level_has_effect() when prim_mode is unknown generated too many SALU. Do this instead: if (triangles) ... subgroup vote for triangles else if (quads) .. subgroup vote for quads else // isoline subgroup vote for isolines Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	2f0d9495c5	ac/nir/tess: inline mask helpers ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	10ae5b2fbf	ac/nir/tess: rewrite tess level tracking, don't use LDS for more cases ... This rewrites tess level value tracking to use the 2-bit masks, which means LDS allocation is determined separately for outer and inner levels. LDS is not allocated for tess levels that are only written by invocation 0 and never read or only read by invocation 0. If the number of output patch vertices is 1, LDS is also not allocated for tess levels. Tess level outputs for TES are always written as whole vec4 to get cached bandwidth. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	9d9cfd89da	ac/nir/tess: compute the number of remapped VRAM outputs in common code ... This unifies it for both drivers. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	ea70060826	ac/nir/tess: stop using tes_inputs_read / tes_patch_inputs read for TCS & TES ... use ac_nir_tess_io_info instead Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	c38bc4824f	ac/nir/tess: apply no_varying to ac_nir_tess_io_info ... This has the effect that no_varying is finally honored for per-patch outputs, skipping VMEM stores that TES doesn't read. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	42445e271e	radv,radeonsi: use ac_nir_tess_io_info for LDS size computation ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	c678844ccb	ac/nir/tess: move LDS and VMEM output masks into a new info structure ... This will replace LDS and VMEM output size computations in drivers. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	f9c2a01f6a	ac/nir/tess: indent a block for nir_if ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	d967266edd	ac/nir/tess: if all tess levels are 0, skip per-vertex TCS output stores ... This is done for all chips. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	c1237256cb	ac/nir/tess: execute the tess level workgroup vote on all chips ... It will be used to skip stores for discarded patches. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	9c16228359	ac/nir/tess: write TCS per-vertex outputs to memory as vec4 stores at the end ... This improves write throughput for TCS outputs. It follows the same idea as attribute stores in hw GS. The improvement is easily measurable with a microbenchmark. It also has the advantage that multiple output stores to the same address don't result in multiple memory stores. Each output components gets only one memory store at the end of the shader. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	509f0e62ad	ac/nir/tess: allow passing explicit patch_offset to VMEM/LDS offset calculations ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	a59464b6e3	radv,radeonsi: precompute and pass TCS per-vertex output stride via a user SGPR ... It's a stride of 1 output, which isn't 16. It's 16 * num_threads, aligned to 256. tcs_offchip_layout has 5 unused bits, so let's use them. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	742227c65c	radv,radeonsi: make TCS_OFFCHIP_LAYOUT_NUM_PATCHES not off by one ... We never use 128 anyway. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	8d3e3c72e0	radv,radeonsi: merge PATCH_CONTROL_POINT & OUT_PATCH_CP into 1 field ... One is only used by TCS, the other is only used by TES. Use the same field for both, call it PATCH_VERTICES_IN. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	534b282573	ac/nir/tess: adjust memory layout of TCS outputs to have aligned store offsets ... There is a comment that explains it. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:38 +00:00
Marek Olšák	80236f2367	ac/nir/tess: add if/endif for HS threads in NIR instead of ACO/LLVM ... This just removes the if/endif wrapping for LLVM, and hopefully the ACO change does the same thing. ACO had redundant code in endif_merged_wave_info, which is removed here. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:38 +00:00
Marek Olšák	cd366b57d9	ac/nir: implement load_subgroup_id/local_invocation_index for TCS on gfx6-10.x ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:38 +00:00
Rhys Perry	86ccceb4de	aco: don't consider gfx1153 to have point sample acceleration ... Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>	2025-06-06 11:55:13 +01:00
Rhys Perry	f10b49781d	aco: make all wait entries linear ... If we remove exec skips, then we can wait for an entry on all paths in the linear cfg, but not the logical cfg. fossil-db (gfx1201): Totals from 0 (0.00% of 79653) affected shaders: fossil-db (navi31): Totals from 0 (0.00% of 79653) affected shaders: fossil-db (navi21): Totals from 1586 (1.99% of 79653) affected shaders: Instrs: 5118897 -> 5113206 (-0.11%); split: -0.11%, +0.00% CodeSize: 28365852 -> 28343696 (-0.08%); split: -0.08%, +0.00% Latency: 47820341 -> 47799532 (-0.04%); split: -0.09%, +0.05% InvThroughput: 9904391 -> 9908653 (+0.04%); split: -0.02%, +0.06% Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>	2025-06-06 11:55:13 +01:00
Rhys Perry	1088ac49db	aco: sometimes join linear wait entries on logical edges ... fossil-db (gfx1201): Totals from 1303 (1.64% of 79653) affected shaders: Instrs: 6920949 -> 6917692 (-0.05%); split: -0.06%, +0.01% CodeSize: 37112404 -> 37095728 (-0.04%); split: -0.05%, +0.01% Latency: 70471343 -> 70365986 (-0.15%); split: -0.15%, +0.00% InvThroughput: 11515673 -> 11504666 (-0.10%); split: -0.10%, +0.01% fossil-db (navi31): Totals from 1293 (1.62% of 79653) affected shaders: Instrs: 6500186 -> 6496761 (-0.05%); split: -0.06%, +0.01% CodeSize: 34562712 -> 34549236 (-0.04%); split: -0.04%, +0.01% Latency: 68604746 -> 68666532 (+0.09%); split: -0.15%, +0.24% InvThroughput: 11276591 -> 11284914 (+0.07%); split: -0.10%, +0.17% fossil-db (navi21): Totals from 811 (1.02% of 79653) affected shaders: Instrs: 4110953 -> 4108788 (-0.05%); split: -0.05%, +0.00% CodeSize: 22955984 -> 22948064 (-0.03%); split: -0.03%, +0.00% Latency: 35070231 -> 35064448 (-0.02%); split: -0.02%, +0.00% InvThroughput: 6945610 -> 6945053 (-0.01%); split: -0.01%, +0.00% Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>	2025-06-06 11:51:08 +01:00
Rhys Perry	c1f8537131	aco: skip waitcnt between two vmem writing different lanes ... fossil-db (gfx1201): Totals from 1382 (1.74% of 79653) affected shaders: Instrs: 6531704 -> 6523935 (-0.12%); split: -0.12%, +0.00% CodeSize: 34992076 -> 34933568 (-0.17%); split: -0.17%, +0.01% Latency: 70183360 -> 69616066 (-0.81%); split: -0.81%, +0.00% InvThroughput: 11155445 -> 11068667 (-0.78%); split: -0.78%, +0.00% fossil-db (navi31): Totals from 46 (0.06% of 79653) affected shaders: Instrs: 1833768 -> 1833732 (-0.00%) CodeSize: 9468788 -> 9468716 (-0.00%) Latency: 11683092 -> 11667865 (-0.13%) InvThroughput: 2274377 -> 2272872 (-0.07%) fossil-db (navi21): Totals from 0 (0.00% of 79653) affected shaders: Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>	2025-06-06 11:51:08 +01:00
Rhys Perry	9649deb50e	aco: skip waitcnt between two vmem writing different halves ... fossil-db (gfx1201): Totals from 4 (0.01% of 79653) affected shaders: Instrs: 41374 -> 41380 (+0.01%); split: -0.01%, +0.02% CodeSize: 238912 -> 238924 (+0.01%); split: -0.01%, +0.01% Latency: 706714 -> 706410 (-0.04%) InvThroughput: 352269 -> 352118 (-0.04%) VClause: 803 -> 798 (-0.62%) fossil-db (navi31): Totals from 0 (0.00% of 79653) affected shaders: fossil-db (navi21): Totals from 0 (0.00% of 79653) affected shaders: Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13028 Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>	2025-06-06 11:51:08 +01:00
Rhys Perry	9a38ad3ca7	aco: add wait_entry::logical_events ... Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>	2025-06-06 11:51:08 +01:00
Rhys Perry	bb99de00f7	aco: add wait_entry::vm_mask ... Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>	2025-06-06 11:51:08 +01:00
Rhys Perry	b70ecfa588	aco: only join barrier_imm/barrier_events for logical edges ... fossil-db (gfx1201): Totals from 3 (0.00% of 79653) affected shaders: Instrs: 2904 -> 2893 (-0.38%) CodeSize: 14944 -> 14900 (-0.29%) Latency: 14703 -> 14248 (-3.09%) InvThroughput: 1237 -> 1210 (-2.18%) fossil-db (navi31): Totals from 3 (0.00% of 79653) affected shaders: Instrs: 2742 -> 2731 (-0.40%) CodeSize: 14136 -> 14092 (-0.31%) Latency: 14744 -> 14287 (-3.10%) InvThroughput: 1241 -> 1213 (-2.26%) fossil-db (navi21): Totals from 3 (0.00% of 79653) affected shaders: Instrs: 2326 -> 2315 (-0.47%) CodeSize: 12472 -> 12428 (-0.35%) Latency: 14921 -> 14465 (-3.06%) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>	2025-06-06 11:51:08 +01:00
Rhys Perry	62a9b4b976	aco: set vmem_types for args_pending_vmem ... fossil-db (gfx1201): Totals from 0 (0.00% of 79653) affected shaders: fossil-db (navi31): Totals from 11 (0.01% of 79653) affected shaders: Instrs: 4543 -> 4554 (+0.24%) CodeSize: 23256 -> 23300 (+0.19%) fossil-db (navi21): Totals from 8 (0.01% of 79653) affected shaders: Instrs: 2333 -> 2341 (+0.34%) CodeSize: 12328 -> 12360 (+0.26%) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Backport-to: 25.0 Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>	2025-06-06 11:51:08 +01:00
Samuel Pitoiset	babeb975c4	radv,radeonsi: fix emitting UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12 ... Not all PFP firmwares for GFX12 have this packet. Fixes: 47f5d25f93 ("radv,radeonsi: emit UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13312 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35370>	2025-06-05 16:51:07 +00:00
Rhys Perry	00a2ed60f8	radv/meta: use unsigned min in copy/fill shaders ... Otherwise, this would break >2 GiB copy/fill. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Backport: 25.1 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35343>	2025-06-05 09:55:32 +00:00
Georg Lehmann	297fdc6636	radv: don't accidentally expose samplerFilterMinmax through Vulkan 1.2 ... Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35339>	2025-06-05 09:01:19 +00:00
Marek Olšák	c3034fa82c	amd: replace most u_bit_consecutive* with BITFIELD_MASK/RANGE ... Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35346>	2025-06-04 17:46:38 +00:00
David Rosca	e579b982b0	radv/video: Set all pic params for H264 encode refs ... Fixes encoding B-frames with I-frame as L1 reference. Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35283>	2025-06-04 11:33:02 +00:00
David Rosca	92e99e6169	radv/video: Add radv_enc_h264/5_pic_type ... Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35283>	2025-06-04 11:33:02 +00:00
Samuel Pitoiset	098c15bfc9	radv: use paired shader registers for graphics on GFX12 ... Loosely based on RadeonSI. This is supposed to be faster because parsing the packet header seems to be the main bottleneck on GFX12. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35282>	2025-06-04 09:17:51 +00:00
Samuel Pitoiset	c8b3c92a3e	radv: add macros for paired shader registers on GFX12 ... Imported from RadeonSI. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35282>	2025-06-04 09:17:51 +00:00
Samuel Pitoiset	c8f9e0fb05	radv: add a new dirty state for emitting tess user SGPRs ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35282>	2025-06-04 09:17:51 +00:00