Commit graph

130 commits

Author SHA1 Message Date
Pierre-Eric Pelloux-Prayer
b7c04b1790 ac/llvm: handle static/shared llvm init separately
Having a single init function works as expected for shared llvm, but
when using a static llvm only one llvm will get initialized.

This commit introduces 2 separate init function:
- shared llvm = single public init function
- static llvm = one init function for each module using llvm

Fixes: 50d20dc055 ("ac/llvm: export ac_init_llvm_once in targets")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3376
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6253>
2020-08-17 10:47:41 +00:00
James Park
24b80f8bb9 amd/llvm: Reorder LLVM headers
LLVM uses __declspec(restrict) which breaks because Mesa define restrict
as __restrict. Move the LLVM headerse up to dodge the macro.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6180>
2020-08-05 17:15:18 +00:00
Rhys Perry
4f3630b36a ac/nir: fix coherent global loads/stores
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6063>
2020-08-05 09:45:54 +00:00
Rhys Perry
4640e7da04 ac/nir: consider an image load/store intrinsic's access
ACCESS_COHERENT may be set for a specific load/store in the case of
atomic loads/stores.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6063>
2020-08-05 09:45:54 +00:00
Rhys Perry
a8f8c02e7e ac/nir: implement scoped_barrier
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5980>
2020-07-29 17:57:13 +00:00
Jason Ekstrand
92dcda5ce9 nir: Add a nir_foreach_function_temp_variable helper
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5966>
2020-07-29 17:38:58 +00:00
Jason Ekstrand
2956d53400 nir: Add nir_foreach_shader_in/out_variable helpers
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5966>
2020-07-29 17:38:57 +00:00
Marek Olšák
abed921ce7 amd: add support for Navy Flounder
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>
2020-07-28 19:47:10 +00:00
Marek Olšák
037b84df11 amd: rename SIENNA -> SIENNA_CICHLID
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>
2020-07-28 19:47:10 +00:00
Samuel Pitoiset
b8517e5ef9 ac/nir: add support for nir_intrinsic_shared_atomic_fadd
Only LLVM 10+ has support.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6000>
2020-07-22 10:20:53 +02:00
Pierre-Eric Pelloux-Prayer
50d20dc055 ac/llvm: export ac_init_llvm_once in targets
If a program like mpv uses both radeon_dri.so (because --vo=gpu) and
radeonsi_drv_video.so (because --hwdec=vaapi) then LLVM will be inialized twice.

The commit exports the ac_init_llvm_once so there's only one instance of the
function.

See also 18b12bf533 ("targets: export radeon winsys_create functions to silence LLVM warning")
which implemented this workaround initially.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1377
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5648>
2020-07-10 11:57:11 +02:00
Pierre-Eric Pelloux-Prayer
438392243f ac/llvm: remove the -1 hack from ac_atomic_inc_wrap
To match the behavior of proprietary drivers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5688>
2020-07-09 09:58:01 +02:00
Bas Nieuwenhuizen
40e00c800c amd/llvm: Mark pointer function arguments as 32-byte aligned.
Otherwise LLVM does not see the pointers as allowing speculative
loads.

The pipeline-db results are pretty wild, but mostly what is to be
expected from allowing more code movement in LLVM:

Totals from affected shaders:
SGPRS: 157728 -> 168336 (6.73 %)
VGPRS: 158628 -> 158664 (0.02 %)
Spilled SGPRs: 10845 -> 24753 (128.24 %)
Spilled VGPRs: 13 -> 13 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 8 -> 8 (0.00 %) dwords per thread
Code Size: 17189180 -> 17313712 (0.72 %) bytes
LDS: 204 -> 204 (0.00 %) blocks
Max Waves: 5700 -> 5687 (-0.23 %)
Wait states: 0 -> 0 (0.00 %)

This gives some boosts for shaders we can move a descriptor load
outside a loop.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3159>
2020-07-08 23:47:06 +00:00
Samuel Pitoiset
f13d79f519 radv: remove the load/store workaround for Monster Hunter World with LLVM
Now that ACO is default, this is pointless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5658>
2020-06-26 14:42:44 +02:00
Marek Olšák
2b8b62c55b ac/nir: fix 64-bit division for GL CTS
This fixes: KHR-GL45.gpu_shader_fp64.builtin.mod_*

Fixes: ba2ec1f3 "ac/nir: use llvm.amdgcn.rcp in ac_build_fdiv()"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5531>
2020-06-23 04:46:55 +00:00
Pierre-Eric Pelloux-Prayer
993c64e6fe ac/llvm: load 1 byte at a time if unaligned on gfx10
If buffer or stride is unaligned we use the same trick as on gfx6:
load 1 byte at a time and recompose the output if needed.
This change fixes lots of deqp/glcts tests:
  - dEQP-GLES2.functional.draw.random.1, 10, ...
  - dEQP-GLES2.functional.vertex_arrays.multiple_attributes.stride.3_float2_0_float2_0_float2_17, ...
  - dEQP-GLES2.functional.vertex_arrays.single_attribute.first.byte_first24_offset1_stride2_quads256, ...
  - dEQP-GLES2.functional.vertex_arrays.single_attribute.strides.buffer_0_17_byte2_vec4_dynamic_draw_quads_1, ...
  - dEQP-GLES31.functional.draw_indirect.random.14, ...

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5502>
2020-06-19 09:20:16 +02:00
Samuel Pitoiset
9b58c4958b ac/nir: fix integer comparisons with pointers
If we get a comparison between a pointer and an integer, LLVM
complains if the operands aren't of the same type.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3085
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5397>
2020-06-10 08:18:22 +00:00
Marek Olšák
9538b9a68e radeonsi: add support for Sienna Cichlid
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
2020-06-09 16:17:36 +00:00
Marek Olšák
2cc4bfbe01 radeonsi: don't set any XNACK options on gfx10.3
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
2020-06-09 16:17:36 +00:00
Marek Olšák
a1602516d7 ac,radeonsi: replace == GFX10 with >= GFX10 where it's needed
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
2020-06-09 16:17:36 +00:00
Samuel Pitoiset
008b0d1701 ac/nir: adjust an assertion for D16 on GFX6-GFX7
16-bit types can be used with MUBUF on GFX6-GFX7.

Fixes: c3e0ba52a0 ("ac/nir: support 16-bit data in buffer_load_format opcodes")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5325>
2020-06-08 08:45:32 +02:00
Marek Olšák
c6c8a9bd55 ac/nir: support v2f16 derivatives
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
2020-06-02 16:29:25 -04:00
Marek Olšák
7c423dd721 ac/nir: set the second v_cvt_pkrtz argument to undef if it's unused
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
2020-06-02 16:29:25 -04:00
Marek Olšák
bfb95725aa ac/nir: select v_cvt_pkrtz for all conversions from f32 to f16 for radeonsi
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
2020-06-02 16:29:25 -04:00
Marek Olšák
1d80015eaf ac/nir: handle nir_op_[fiu]2[fiu]mp opcodes
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
2020-06-02 16:29:25 -04:00
Marek Olšák
70b6d54011 ac/nir: support 16-bit data in image opcodes
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
2020-06-02 16:29:25 -04:00
Marek Olšák
c3e0ba52a0 ac/nir: support 16-bit data in buffer_load_format opcodes
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
2020-06-02 16:29:25 -04:00
Marek Olšák
b819ba949b ac/nir: remove type and num_channels args from ac_build_buffer_store_common
They were only used for type overloading where we can just use
the type of data.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
2020-06-02 16:29:25 -04:00
Marek Olšák
b98df7bf50 ac/nir: support vector types in the type suffix of overloaded intrinsics
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
2020-06-02 16:29:25 -04:00
Marek Olšák
e5ea87cde8 ac/nir: use more types from ac_llvm_context
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
2020-06-02 16:29:25 -04:00
Dylan Baker
a8e2d79e02 meson: use gnu_symbol_visibility argument
This uses a meson builtin to handle -fvisibility=hidden. This is nice
because we don't need to track which languages are used, if C++ is
suddenly added meson just does the right thing.

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4740>
2020-06-01 18:59:18 +00:00
Samuel Pitoiset
e99c818cf0 ac/nir: add support for bias/lod with texture gather
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5147>
2020-05-25 08:51:10 +02:00
Samuel Pitoiset
14292310d9 ac/nir: implement nir_intrinsic_shader_clock with device scope
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5117>
2020-05-24 20:37:58 +02:00
Samuel Pitoiset
b034f6cf2a ac/nir: fix shader clock with subgroup scope
The compiler should emit s_memtime instead of s_memrealtime for
the subgroup scope. I don't know why this LLVM 9 checks was for
but LLVM 8 also has this amdgcn intrinsic.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5117>
2020-05-24 20:37:54 +02:00
Michel Dänzer
2a6811f0f9 Revert "ac,radeonsi: fix compilations issues with LLVM 11"
This reverts commit 42b1696ef6.

The corresponding LLVM changes were reverted.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5087>
2020-05-19 07:19:35 +00:00
Marek Olšák
2361e8e722 ac/nir: honor ACCESS_STREAM_CACHE_POLICY for L1 and L0 caches too
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
2020-05-15 22:12:35 +00:00
Samuel Pitoiset
0d63a1a84d ac/llvm: add support for texturing with clamped LOD
This is a requirement for the shaderResourceMinLod feature which
allows to clamp LOD. This uses all image_sample_*_cl variants.

All dEQP-VK.glsl.texture_functions.texture*clamp.* pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4989>
2020-05-14 10:05:44 +00:00
Pierre-Eric Pelloux-Prayer
ae4379d81e ac/nir: export some undef as zero
NIR already optimizes undef usage.
If undef reaches llvm, it's probably because of a broken shader.

In this situation, rather than letting llvm use the undef values
to do more optimization and probably produce incorrect results,
we replace undef values by 0.

"undef" values that are directly used in exports are kept as undef,
because this allows llvm to optimize them away.

This is only enabled for radeonsi.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2689
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
2020-05-05 12:26:26 +02:00
Pierre-Eric Pelloux-Prayer
64662dd5ba radeonsi: add workaround for issue 2647
For unknown reasons pixel shaders in KSP game get executed with
infinite interpolation coefficients and this causes an infinite
loop in the shader.

This commit adds a hacky workaround that kills pixel shaders if
invalid interp coeffs are detected and enables it for KSP.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2174
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2647
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4700>
2020-05-05 09:41:14 +00:00
Marek Olšák
b97cc41aa2 Revert "ac: reassociate FP expressions for inexact instructions for radeonsi"
This reverts commit cf2f3c2753.

It breaks shadows in Unigine Superposition.

Fixes: cf2f3c2753

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4837>
2020-05-04 11:51:37 -04:00
Pierre-Eric Pelloux-Prayer
7e7bb38bd8 radeonsi: fix export count
Fixes: 17acff01a0 ("radeonsi: skip vs output optimizations for some outputs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2877
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4871>
2020-05-04 15:11:09 +02:00
Samuel Pitoiset
aa94213781 ac/llvm: fix nir_texop_texture_samples with NULL descriptors
With VK_EXT_robustness2, descriptors can be NULL and the number of
samples returned by nir_texop_texture_samples should be 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4775>
2020-04-29 07:29:54 +00:00
Samuel Pitoiset
42b1696ef6 ac,radeonsi: fix compilations issues with LLVM 11
Latest LLVM replaced LLVMVectorTypeKind.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2826
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4755>
2020-04-27 17:13:36 +00:00
Marek Olšák
cf2f3c2753 ac: reassociate FP expressions for inexact instructions for radeonsi
Totals:
SGPRS: 2591784 -> 2590696 (-0.04 %)
VGPRS: 1666888 -> 1666736 (-0.01 %)
Spilled SGPRs: 4131 -> 4107 (-0.58 %)
Spilled VGPRs: 38 -> 38 (0.00 %)
Private memory VGPRs: 2176 -> 2176 (0.00 %)
Scratch size: 2228 -> 2228 (0.00 %) dwords per thread
Code Size: 52715468 -> 52693584 (-0.04 %) bytes
LDS: 92 -> 92 (0.00 %) blocks
Max Waves: 479897 -> 479892 (-0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4696>
2020-04-27 11:20:16 +00:00
Marek Olšák
4b9370cb0f ac: generate FMA for inexact instructions for radeonsi
NIR mostly does this already.

Totals:
SGPRS: 2588520 -> 2591784 (0.13 %)
VGPRS: 1666984 -> 1666888 (-0.01 %)
Spilled SGPRs: 4074 -> 4131 (1.40 %)
Spilled VGPRs: 38 -> 38 (0.00 %)
Private memory VGPRs: 2176 -> 2176 (0.00 %)
Scratch size: 2228 -> 2228 (0.00 %) dwords per thread
Code Size: 52726872 -> 52715468 (-0.02 %) bytes
LDS: 92 -> 92 (0.00 %) blocks
Max Waves: 479872 -> 479897 (0.01 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4696>
2020-04-27 11:20:16 +00:00
Marek Olšák
f2c2a28073 ac: update and document fast math flags used by radeonsi
This should have no effect, because we never use FP division, but
it's safer for the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4696>
2020-04-27 11:20:16 +00:00
Marek Olšák
3bb65c0670 ac: force enable -structurizecfg-skip-uniform-regions for LLVM 11
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4696>
2020-04-27 11:20:16 +00:00
Marek Olšák
b4fd8f1919 ac,radeonsi: simplify checking for Navi1x chips
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4698>
2020-04-24 10:38:54 +00:00
Pierre-Eric Pelloux-Prayer
17acff01a0 radeonsi: skip vs output optimizations for some outputs
If PT_SPRITE_TEX is enabled, PS inputs are overriden at runtime so
we can't apply the vs output optim.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2747
Fixes: 3ec9975555 ("radeonsi: eliminate trivial constant VS outputs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4559>
2020-04-20 08:45:16 +02:00
Samuel Pitoiset
9f005f1f85 radv: enable lowering of GS intrinsics for the LLVM backend
This replaces emit_vertex with:
   if (vertex_count < max_vertices) {
      emit_vertex_with_counter vertex_count ...
      vertex_count += 1
   }

Which is exactly what NIR->LLVM was doing but at NIR level. This
pass is already called by ACO.

pipeline-db changes on GFX10:
Totals from affected shaders:
SGPRS: 1952 -> 1912 (-2.05 %)
VGPRS: 2112 -> 2044 (-3.22 %)
Code Size: 189368 -> 185620 (-1.98 %) bytes
Max Waves: 494 -> 491 (-0.61 %)

No pipeline-db changes on other generations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4182>
2020-04-08 08:24:05 +02:00